Abstract: To load compacted memory between a system memory and a local data share (LDS), a processing system includes an accelerator unit (AU) connected to a memory unit. The memory unit is configured to identify that compacted data in the system memory is to be written to elements of an LDS based on two or more compaction masks. The memory unit is configured to then determine sources within the memory from which to load compacted data into the elements of the LDS by determining pre-fix sums based on the two or more compaction masks. The memory unit is configured to then load the compacted data from the identified sources to corresponding elements of the LDS.

Abstract: Systems and methods for faster BVH building that requires repeated sorting and partitioning of are described. Specific hardware circuitries are programmed to sort partitioned data and make reductions for each partition. The hardware units perform the initial sorting along a split axis and calculation of bounding box extents. The solutions presented herein improve performance of BVH builds, especially for cases where the geometry is comprised of many small BVH treelets. The most expensive processing steps in BVH construction are delegated to hardware thereby minimizing memory access latencies and increasing overall system efficiencies.

Abstract: A processing unit processes primitives in a hardware accelerated mode. In the hardware accelerated mode the processing unit employs a mesh shader to provide primitives to other stages of a graphics pipeline as a set of four vertices, with each of the four vertices representing the vertex of a corresponding quad. In some cases, one or more of the vertices provided by the mesh shader is referenced by multiple quad primitives. The rasterizer of the graphics pipeline processes each quad primitive as a set of two triangles, but in the hardware accelerated mode, pixel shader operations are provided with vertex data from all four vertices of the corresponding quad primitive.

Abstract: To load compacted memory between a system memory and a local data share (LDS), a processing system includes an accelerator unit (AU) connected to a memory unit. The memory unit is configured to identify that compacted data in the system memory is to be written to elements of an LDS based on two or more compaction masks. The memory unit is configured to then determine sources within the memory from which to load compacted data into the elements of the LDS by determining pre-fix sums based on the two or more compaction masks. The memory unit is configured to then load the compacted data from the identified sources to corresponding elements of the LDS.

Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.