Abstract: A circuit divides pulse code modulation (PCM) samples in D2 format. An exponent subtractor provides the difference of the exponents of the two numbers. A mantissa multiplier circuit determines the quotient by multiplying the mantissa of the PCM sample by an inverted divider. A sign generator provides a sign value for the resultant quotient of the two numbers. A normalizer circuit ensures that the quotient mantissa has a predetermined range of values.

Abstract: A circuit multiplies or divides pulse code modulation (PCM) samples in D2 format. An exponent adder/subtractor provides the sum/difference of the exponents of the two numbers. A mantissa multiplier/divider circuit determines the product/quotient of the two mantissas and a sign generator provides a sign value for the resultant product/quotient of the two numbers. A normalizer circuit ensures that the product/quotient mantissa has a predetermined range of values.

Abstract: A circuit multiplies pulse code modulation (PCM) samples in D2 format. An exponent adder provides the sum of the exponents of the two numbers. A mantissa multiplier circuit determines the product of the two mantissas and a sign generator provides a sign value for the resultant product of the two numbers. A normalizer circuit ensures that the product mantissa has a predetermined range of values.

Abstract: A circuit adds and subtracts pulse code modulation (PCM) samples in D2 format. An exponent subtractor determines the difference between exponents of the two PCM samples. A mantissa shifter circuit shifts the mantissa portion of a selected PCM sample to compensate for the difference in the exponents. A mantissa adder circuit adds or subtracts the mantissa portion of the shifted and unshifted PCM samples and a sign generator provides a sign value representative of the resultant added or subtracted PCM samples. A normalizer circuit ensures that the mantissa has a predetermined range of values.

Abstract: A clock selection circuit which selects and enables one of a plurality of clock circuits in response to initialization by a processing unit or detection of failure of an on-line clock circuit. The clock circuits are selected on the basis of a priority arrangement. The clock circuit failure is detected by a retriggerable monostable multivibrator and the selection priority is based on time delays generated by programmed counters associated with each clock circuit.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A circuit which controls the selection and activation of one of a plurality of clock circuits arranged in copies. Selection circuitry is used to detect failure of an on-line clock circuit, scan a plurality of available clock circuits in a predetermined sequence and place the next available properly operating clock circuit on line. Control circuitry prevents erroneous clock selection during power-up/power down operations and enables predetermined clock circuit copies to be disabled.

Abstract: A circuit which selects and enables one of a plurality of clock circuits. Logic circuitry is used to detect failure of an on line clock circuit, scan a plurality of available clock circuits in a predetermined sequence and place the next available properly operating clock circuit on line.

Abstract: A direct current compensation circuit is provided for use with a transformer having a plurality of windings. A resistor is connected in series with a first winding. A transistor is coupled to the first resistor and to a compensation winding so that when the direct current flow through the resistor is greater than a predetermined value, a compensation current is supplied to the compensation winding. When the direct current flow through the resistor is less than the predetermined value, no compensation current is supplied to the compensation winding.

Abstract: A circuit for use with a transformer having a plurality of windings monitors the direct current flow through a first winding and provides a corresponding compensation current to a second winding. The circuit also provides an output signal indicating whether the magnitude of the compensation current is greater than or less than a predetermined magnitude.