Patents by Inventor Max Strasburg
Max Strasburg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9601498Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: GrantFiled: May 23, 2011Date of Patent: March 21, 2017Assignee: Nantero Inc.Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Max Strasburg, Frank Guo, X. M. Henry Huang, Ramesh Sivarajan
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Patent number: 8580586Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.Type: GrantFiled: January 15, 2009Date of Patent: November 12, 2013Assignee: Nantero Inc.Inventors: Claude L. Bertin, Frank Guo, Thomas Rueckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Henry Huang
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Publication number: 20110220859Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, Mitchell MEINHOLD, Steven L. KONSEK, Thomas RUECKES, Max STRASBURG, Frank GUO, X. M. Henry HUANG, Ramesh SIVARAJAN
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Patent number: 7986546Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.Type: GrantFiled: June 30, 2008Date of Patent: July 26, 2011Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Frank Guo, Thomas Rueckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Henry Huang
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Patent number: 7948054Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: GrantFiled: August 23, 2010Date of Patent: May 24, 2011Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Max Strasburg, Frank Guo, X. M. Henry Huang, Ramesh Sivarajan
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Publication number: 20110044091Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: ApplicationFiled: August 23, 2010Publication date: February 24, 2011Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, Mitchell MEINHOLD, Steven L. KONSEK, Thomas RUECKES, Max STRASBURG, Frank GUO, X. M. Henry HUANG, Ramesh SIVARAJAN
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Patent number: 7781862Abstract: A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: GrantFiled: November 15, 2005Date of Patent: August 24, 2010Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Ruckes, Max Strasburg, Frank Guo, X. M. Henry Huang, Ramesh Sivarajan
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Publication number: 20090154218Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.Type: ApplicationFiled: January 15, 2009Publication date: June 18, 2009Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, Frank GUO, Thomas RUECKES, Steven L. KONSEK, Mitchell MEINHOLD, Max STRASBURG, Ramesh SIVARAJAN, X. M. Henry HUANG
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Publication number: 20090052246Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.Type: ApplicationFiled: June 30, 2008Publication date: February 26, 2009Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, Frank GUO, Thomas RUECKES, Steven L. KONSEK, Mitchell MEINHOLD, Max STRASBURG, Ramesh SIVARAJAN, X. M. HUANG
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Patent number: 7479654Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.Type: GrantFiled: November 15, 2005Date of Patent: January 20, 2009Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Frank Guo, Thomas Rueckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Henry Huang
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Patent number: 7394687Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.Type: GrantFiled: November 15, 2005Date of Patent: July 1, 2008Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Frank Guo, Thomas Ruckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. H. Huang
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Publication number: 20080012047Abstract: A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: ApplicationFiled: November 15, 2005Publication date: January 17, 2008Applicant: Nantero, Inc.Inventors: Claude Bertin, Mitchell Meinhold, Steven Konsek, Thomas Ruckes, Max Strasburg, Frank Guo, X. M. Huang, Ramesh Sivarajan
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Publication number: 20060250856Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.Type: ApplicationFiled: November 15, 2005Publication date: November 9, 2006Applicant: Nantero, Inc.Inventors: Claude Bertin, Frank Guo, Thomas Rueckes, Steven Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Huang
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Publication number: 20060250843Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.Type: ApplicationFiled: November 15, 2005Publication date: November 9, 2006Applicant: Nantero, Inc.Inventors: Claude Bertin, Frank Guo, Thomas Rueckes, Steven Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X.M. Huang