Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.

Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.

Abstract: A circuit includes a first driver, a second driver, and a burst mode control circuit coupled to the first and second drivers. The burst mode control circuit is configured to implement a burst mode operation having a burst soft-on portion and a burst portion. During the soft-on portion of the burst mode operation, the burst mode control circuit is configured to cause the first and second drivers to produce a first set of pulses of increasing pulse width. During the burst portion of the burst mode operation, the burst mode control circuit is configured to cause the first and second drivers to produce a second set of pulses of a constant pulse width.

Abstract: A circuit includes a first driver, a second driver, and a burst mode control circuit coupled to the first and second drivers. The burst mode control circuit is configured to implement a burst mode operation having a burst soft-on portion and a burst portion. During the soft-on portion of the burst mode operation, the burst mode control circuit is configured to cause the first and second drivers to produce a first set of pulses of increasing pulse width. During the burst portion of the burst mode operation, the burst mode control circuit is configured to cause the first and second drivers to produce a second set of pulses of a constant pulse width.

Abstract: Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.

Abstract: Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.