Abstract: In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.

Abstract: An integrated circuit includes at least one first magnetic field sensing element including at least one first magnetoresistance element configured to provide an output signal of the integrated circuit in response to a detected magnetic field. The integrated circuit also includes at least one second magnetic field sensing element including at least one second magnetoresistance element configured to have a characteristic indicative of a stress condition. A method for detecting a stress condition in an integrated circuit is also provided.

Abstract: An integrated circuit device includes a package and at least two leads exposed external to the package to permit electrical connections to the package. A first die situated in the package has a first substrate and at least a first terminal electrically coupled to a first one of the leads. A second die situated in the package has a second substrate and at least a second terminal electrically coupled to a second one of the lead. An adhesive material holding the first and second die in place forms a voltage-triggered conduction path between the first and second die electrically that isolates the second die from the first die under a first condition and provides an ESD current path between the first one of the leads and the second one of the leads under a second condition.

Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

Abstract: In an embodiment, an electronic device comprises a shared electrical over-stress (EOS) protection circuit. The shared EOS protection circuit may be coupled between a power input terminal and ground terminal to provide an EOS current path from the power input terminal to the ground terminal, and coupled between the output terminal and the ground terminal to provide an EOS current path from the output terminal to the ground terminal. The electronic device may also include a power interruption mitigation circuit to provide power to the electronic device during interruptions or fluctuations in external power.

Abstract: In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

Abstract: A power clamp circuit having improved robustness to electrostatic discharge (ESD) events includes a voltage regulation circuit and a current controlled switch. The voltage regulation circuit and the current controlled switch may be used to modify a snapback voltage of the power clamp in a manner that enhances the power clamp's ability to handle ESD events.

Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit may be coupled to the driver circuit for controlling the driver circuit. A transistor may be coupled in series between the driver circuit and the output terminal. The transistor may have a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit may be coupled to a gate terminal of the transistor and configured to bias the transistor to a conducting state. The biasing circuit may have sufficient drive strength to maintain the transistor in the conducting state in the presence of electromagnetic interference.

Abstract: A power clamp circuit having improved robustness to electrostatic discharge (ESD) events includes a voltage regulation circuit and a current controlled switch. The voltage regulation circuit and the current controlled switch may be used to modify a snapback voltage of the power clamp in a manner that enhances the power clamp's ability to handle ESD events.