Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

Abstract: A method is described that includes monitoring degradation of a semiconductor chip's transistors during normal operation. The method further includes raising an internal voltage of the semiconductor chip in response to the degradation. The method further includes determining that the degradation has reached a threshold. The method further includes triggering application of an elevated temperature to the semiconductor chip so that the degradation is at least partially reversed. The method further includes applying a new lower internal voltage of the semiconductor chip in account of the degradation reversal.

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

Abstract: A method is described that includes monitoring degradation of a semiconductor chip's transistors during normal operation. The method further includes raising an internal voltage of the semiconductor chip in response to the degradation. The method further includes determining that the degradation has reached a threshold. The method further includes triggering application of an elevated temperature to the semiconductor chip so that the degradation is at least partially reversed. The method further includes applying a new lower internal voltage of the semiconductor chip in account of the degradation reversal.

Abstract: Provided is an approach to saving active power through lowering a supply voltage when operating temperature goes up, while substantially maintaining operating performance.

Abstract: Reducing power to a minimum permissible value based on temperature of a component may permit savings in power consumption.

Abstract: Reducing power to a minimum permissible value based on temperature of a component may permit savings in power consumption.

Abstract: A semiconductor die may include circuitry and a circuit designed to provide protection to the circuitry from an electrostatic discharge coming into the semiconductor die through an input/output pad of the semiconductor die. The circuit may be physically coupled to the input/output pad by a coupling device. When the coupling device is in a first state, the circuit may be electrically coupled to the circuitry and the input/output pad, and when the coupling device is in a second state, the circuit may be electrically decoupled from the circuitry and the input/output pad.