Abstract: An electric vehicle powertrain is disclosed. The powertrain includes an electric motor electrically coupled to an energy storage system That includes a motor control unit to determine a phase of the electric motor and a plurality of cells to determine a discrete power output based, at least in part, on the determined phase of the electric motor; and generate the determined discrete power output. The energy storage system includes a power bank management unit to determine an overall power output based, at least in part, on the determined phase of the electric motor; determine a subset of the plurality of cells based, at least in part, on the overall power output; and command each cell of the subset of the plurality of cells to generate the discrete power output, the subset of the plurality of cells to collectively generate an output equal to the overall power output.

Abstract: A scalable and manageable energy storage system and methods are disclosed. By accounting for the characteristics of an individual cell in a battery, the disclosed system and method prevents cell stress to extend the useful life span of the cell. A dynamic wiring topology allows the scalable and manageable energy storage system to directly control a load or be charged by a volatile energy source.

Abstract: A network device includes a network interface circuit, a microprocessor, a timing circuit, and a microsequencer. The timing circuit is configured to, based on a primary timing signal, generate a time signature and switch the network device from an inactive state to an active state when the time signature satisfies a predetermined threshold length of time for packet transmission. The microsequencer circuit is configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor. The device also reduces energy consumption by using a lower frequency secondary oscillator to maintain timing information when a higher frequency primary oscillator is inactivated.

Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

Abstract: The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.

Abstract: Correcting a time of reception of a data packet is disclosed. A radio-frequency input is converted to a data-output signal. A data clock is recovered from the data-output signal. A phase offset is measured between the data-output signal and the data clock. A time of reception is corrected based at least in part on a timestamp. The timestamp is a sampled value of a counter at a time of reception of a data packet and the phase offset. The time correction can be used to calculate a distance estimate.

Abstract: The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.