Patents by Inventor Maxime GARCIA-BARROS

Maxime GARCIA-BARROS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658197
    Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: May 19, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Nicolas Posseme, Maxime Garcia-Barros, Yves Morand
  • Patent number: 9947541
    Abstract: A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x?0.2, and having a pH less than or equal to 1.5.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 17, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Pollet, Maxime Garcia-Barros, Nicolas Posseme
  • Publication number: 20180012766
    Abstract: A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x?0.2, and having a pH less than or equal to 1.5.
    Type: Application
    Filed: June 20, 2017
    Publication date: January 11, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Pollet, Maxime Garcia-Barros, Nicolas Posseme
  • Patent number: 9780000
    Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate; depositing a layer comprising carbon, said layer being disposed distant from said transistor; modifying the protective layer to form a modified protective layer; forming a protective film on the layer comprising carbon; removing the protective film on surfaces of the protective film that are perpendicular to a main implantation direction; selectively removing the layer comprising carbon; and at least one step of selectively removing the modified protective layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Maxime Garcia-Barros
  • Publication number: 20170186623
    Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 29, 2017
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Nicolas POSSEME, Maxime Garcia-Barros, Yves Morand
  • Publication number: 20170154826
    Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate; depositing a layer comprising carbon, said layer being disposed distant from said transistor; modifying the protective layer to form a modified protective layer; forming a protective film on the layer comprising carbon; removing the protective film on surfaces of the protective film that are perpendicular to a main implantation direction; selectively removing the layer comprising carbon; and at least one step of selectively removing the modified protective layer.
    Type: Application
    Filed: November 25, 2016
    Publication date: June 1, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Maxime GARCIA-BARROS