Patents by Inventor Maxime Jean Rattier
Maxime Jean Rattier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7616904Abstract: A germanium on silicon waveguide photodetector disposed on a silicon on insulator (SOI) substrate. The photodetector is incorporated into a section of a planar silicon waveguide on the substrate. The photodetector generates an electric current as an infrared optical signal travels through the photodetector.Type: GrantFiled: February 23, 2007Date of Patent: November 10, 2009Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Giovanni Capellini
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Patent number: 7586608Abstract: This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.Type: GrantFiled: March 28, 2007Date of Patent: September 8, 2009Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Roman Malendevich, Thierry J. Pinguet, Maxime Jean Rattier, Myles Sussman, Jeremy Witzens
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Patent number: 7453132Abstract: A germanium on silicon waveguide photodetector disposed on a silicon on insulator (SOI) substrate. The photodetector is incorporated into a section of a planar silicon waveguide on the substrate. The photodetector generates an electric current as an infrared optical signal travels through the photodetector.Type: GrantFiled: June 19, 2003Date of Patent: November 18, 2008Assignee: Luxtera Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Giovanni Capellini
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Patent number: 7262852Abstract: This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.Type: GrantFiled: November 14, 2005Date of Patent: August 28, 2007Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Roman Malendevich, Thierry J. Pinguet, Maxime Jean Rattier, Myles Sussman, Jeremy Witzens
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Patent number: 7260293Abstract: Various configurations of elongate scattering elements in an optical waveguide grating coupler for coupling light between a planar waveguide and an optical element such as an optical fiber, where the light may have a Gaussian intensity distribution. The elongate scattering elements are preferably curved, and in some embodiments, the scattering elements have elliptically curved shape. One or more of the elongate scattering elements may be segmented into various geometrical shapes, such as rectangular, square, circular and elliptical. The elongate scattering elements have at least one characteristic selected from the group consisting of grating width, height, spacing, depth and index of refraction forming the elongate scattering elements, where the magnitude of the at least one characteristic varies irregularly with position along the guiding portion of the optical waveguide grating coupler.Type: GrantFiled: December 6, 2005Date of Patent: August 21, 2007Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7251403Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 15, 2005Date of Patent: July 31, 2007Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7231105Abstract: An apparatus and method for splitting a received optical signal into its orthogonal polarizations and sending the two polarizations on separate dual integrated waveguides to other systems on chip for further signal processing. The present invention provides an apparatus and method for facilitating the processing of optical signals in planar waveguides received from optical fibers.Type: GrantFiled: March 17, 2006Date of Patent: June 12, 2007Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7218826Abstract: A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. FIG. 12 shows an active waveguide formed by a standard CMOS process on a five layer substrate. The waveguide is a silicon strip loaded waveguide with a three layer core made of a silicon strip on a silicon slab with a silicon dioxide layer between the strip and slab. The active waveguide has two doped regions in the silicon slab adjacent to and on either side of the waveguide. FIG. 12A is a table summarizing the elements of the waveguide of FIG. 12 and the CMOS transistors of FIGS. 1 and 2, which are formed from the same materials at the same time on the same silicon substrate. In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors.Type: GrantFiled: August 29, 2005Date of Patent: May 15, 2007Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Bing Li
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Patent number: 7184627Abstract: An optical wavelength grating coupler incorporating one or more distributed Bragg reflectors (DBR) or other reflective elements to enhance the coupling efficiency thereof. The grating coupler has a grating comprising a plurality of scattering elements adapted to scatter light along a portion of an optical path, and the one or more DBRs are positioned with respect to the grating such that light passing through the grating towards the substrate of the grating coupler is reflected back by DBRs toward the grating. The DBR comprises a multilayer stack of various materials and may be formed on the substrate of the grating coupler. The grating coupler may include a gas-filled cavity, where the cavity is formed by a conventional etching process and is used to reflect light toward the grating. The grating coupler may also incorporate an anti-reflection coating to reduce reflective loss on the surface of the grating.Type: GrantFiled: November 16, 2005Date of Patent: February 27, 2007Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7136563Abstract: A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a two layer core made of a polysilicon strip on a silicon slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.Type: GrantFiled: July 7, 2005Date of Patent: November 14, 2006Assignee: Luxtera Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7116881Abstract: A standard CMOS process is modified to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a three layer core made of a polysilicon strip on a silicon slab with a silicon dioxide layer between the strip and the slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.Type: GrantFiled: July 7, 2005Date of Patent: October 3, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7095936Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical devices such as the core of an optical waveguide or a light scatterer will damage the devices and prevent the passage of light through those sections of the devices. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 14, 2005Date of Patent: August 22, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7082246Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 15, 2005Date of Patent: July 25, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7082247Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: August 29, 2005Date of Patent: July 25, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Jeremy Witzens, Zhen-Li Ji
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Patent number: 7082245Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 15, 2005Date of Patent: July 25, 2006Assignee: Luxtern, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7079742Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 15, 2005Date of Patent: July 18, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7072556Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: August 29, 2005Date of Patent: July 4, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Bing Li
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Patent number: 7068887Abstract: A polarization splitting grating coupler (PSGC) connects an optical signal from an optical element, such as a fiber, to an optoelectronic integrated circuit. The PSGC separates a received optical signal into two orthogonal polarizations and directs the two polarizations to separate waveguides on an integrated circuit. Each of the two separated polarizations can then be processed, as needed for a particular application, by the integrated circuit. A PSGC can also operate in the reverse direction, and couple two optical signals from an integrated circuit to two respective orthogonal polarizations of one optical output signal sent off chip to an optical fiber.Type: GrantFiled: October 26, 2005Date of Patent: June 27, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Jeremy Witzens
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Patent number: 7058273Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 14, 2005Date of Patent: June 6, 2006Assignee: Luxtera, Inc.Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
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Patent number: 7054534Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.Type: GrantFiled: July 15, 2005Date of Patent: May 30, 2006Assignee: Luxtera, IncInventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier