Abstract: Methods and systems for repurposing of a global navigation satellite system receiver for receiving low-earth orbit (LEO) communication satellite timing signals may comprise receiving medium Earth orbit (MEO) satellite signals and/or LEO signals in a receiver of the communication device. A radio frequency (RF) path may be configured to down-convert either of the signals, and a position of the communication device may be calculated utilizing the down-converted signals. The signals may be down-converted utilizing a local oscillator signal generated by a phase locked loop (PLL), which may be delta-sigma modulated via a fractional-N divider. A clock signal may be communicated to the PLL utilizing a temperature-compensated crystal oscillator. The signals may be down-converted to an intermediate frequency or down-converted directly to baseband frequencies. The signals may be processed utilizing surface acoustic wave (SAW) filters.

Abstract: Methods and systems for a dual mode global navigation satellite system may comprise selectively enabling a medium Earth orbit (MEO) radio frequency (RF) path and a low Earth orbit (LEO) RF path in a wireless communication device to receive RF satellite signals. The signals may be down-converted to determine a position of the wireless device. The signals may be down-converted utilizing local oscillator signals from a phase locked loop (PLL). The RF paths may be time-division duplexed by the selective enabling of the MEO and LEO paths. Acquisition and tracking modules in the MEO RF path may be blanked when the LEO RF path is enabled. The MEO RF path may be powered down when the LEO RF path is enabled. The signals may be down-converted to an intermediate frequency before down-converting to baseband frequencies or may be down-converted directly to baseband frequencies. In-phase and quadrature signals may be processed.

Abstract: Methods and systems for indoor global navigation satellite system detection utilizing low Earth orbit satellite signals may comprise receiving low Earth orbit (LEO) RF satellite signals utilizing a LEO satellite signal receiver path (LEO Rx) in a wireless communication device comprising the LEO satellite signal receiver path and a medium Earth orbit satellite signal receiver path (MEO Rx). A received signal strength indicator (RSSI) may be measured for the received LEO signals and an expected received MEO signal strength may be calculated. A power level of the MEO Rx may be configured based on the calculated MEO signal strength by powering down when the calculated expected MEO signal strength is below a threshold level for MEO positioning purposes and/or powered up when it increases above the threshold level. The RSSI may be measured at a plurality of points along the LEO Rx.

Abstract: Methods and systems for global navigation satellite system configuration of wireless communication applications may comprise determining a location of a wireless communication device (WCD) comprising a medium Earth orbit (MEO) radio frequency (RF) path and a low Earth orbit (LEO) RF path utilizing received LEO signals. A wireless function of the WCD may be configured based on the location, and may comprise a power level of WiFi circuitry in the WCD. The determined location and a transaction ID for the POS transaction may be stored utilizing a security processor. The MEO RF path may be powered down based on the determined location. The wireless function may comprise a synchronization of data on the WCD with devices in a home location. The WCD may comprise a femtocell device or a set-top box, and may be controlled by a reduced instruction set computing (RISC) central processing unit (CPU).

Abstract: A power-saving GNSS includes a sensor for detecting a motion of the receiver, an RF front-end for receiving satellite signals, and a central processing unit coupled to the front-end for acquiring a set of the received satellite signals if the motion is detected. The receiver further include a signal strength evaluator for evaluating a signal strength of the acquired set of the received signals and a counter to count a time period for which the signal strength is below a predetermined value. The receiver also includes a control unit for setting the receiver into an intermittent operating mode if the signal strength exceeds the predetermined value sets the receiver into a power-saving mode if the signal strength is below the predetermined value for the time period determined by the counter. The receiver may also be set into the power-saving mode if it remains stationary for a given time interval.

Abstract: A GNSS receiver includes a radio frequency module and an antenna for acquiring and tracking signals from various satellites and demodulating them to an intermediate frequency or a baseband signal. The receiver also includes a processing unit for processing the demodulated signals to obtain a first position, velocity, and time (PVT fix) data and displays the data to a user. The receiver may include a memory unit for storing the obtained PVT fix. The receiver may further include one or more sensors for detecting a motion of the receiver and provide an index to the processing unit that determines a next position of the receiver based on the index during a coverage gap. The one or more sensors may include an accelerometer, a compass, or a combination thereof.

Abstract: A GNSS receiver includes a sensing element for detecting an environmental condition, a control unit for dynamically calculating a sleep time duration in response to the environmental condition, and a digital processing unit that operates in a first mode or in a second mode based on the calculated sleep time duration and the environmental condition. The environmental condition may include a receiver signal strength indicator, a receiver velocity, the stability and precision of a local reference clock, a recent almanac, an ephemeris data, and the like. The first operation mode may include a tracking of satellite signals, and the second operation mode may include an acquisition operation, a tracking operation, or a combination of acquisition and tracking operations of satellite signals.

Abstract: A method for securely generating and distributing encryption keys includes generating, by a secured server, a pair of keys including a first key and a second key and providing, by a key distributing unit, the first key to a first recipient and a second key to a second recipient. The first recipient may use the first key to encrypt a data file and send the encrypted data file via a non-volatile memory device to a target subscriber. The second recipient may program the second key into an one-time-programmable register contained in a secure element during a manufacturing process. The secure element may further include a random access memory configured to store an image of the encrypted data file, a read-only memory containing a boot code, and a processing unit coupled to the random-access memory and the read-only memory and operative to decrypt the encrypted data file.

Abstract: A system and method for improving acquisition sensitivity and tracking performance of a GPS receiver using multiple antennas is provided. In an embodiment, the acquisition sensitivity can be improved by determining the correlation weight of each received path signal path associated with one antenna form a plurality of antennas and then combining the path signals based on their respective correlation weight. In another embodiment, carrier offset correction information of each path signal is individually determined and then summed together to be used for tracking the code phase in a code phase tracking loop. The code phase tracking loop generates an early code and a late code that are used to determine the code phase error. The system includes notch and bandpass filters to mitigate narrowband and broadband noises of a received GPS signal, wherein the digital adaptive filters are switched on periodically or by external events.

Abstract: A device for descrambling encrypted data includes a descrambler, a secure link, and a secure element that securely transmits a control word to the descrambler in a normal operating mode. The secure element includes a first secure register, a read-only memory having a boot code, a random-access memory for storing a firmware image from an external memory, and a processor coupled to the first secure register, the read-only memory, and the random access memory. The processor executes the boot code to generate the control word, stores the control word in the first secure register, and send the stored control word to the descrambler through a secure communication link. The descrambler may include a second secure register that is connected to the first secure register through the secure link. The first and second secure registers are not scannable during a normal operation. The secure link contains buried signal traces.

Abstract: A method of generating an encryption key during the manufacturing process of a device includes randomly generating a seed, encrypting a unique identifier disposed in the device to obtain a first encryption key, encrypting the first encryption key using a public key to obtain a second encryption key, and sending the second encryption key and the seed to a software provider. The method further includes receiving the second encryption key and the seed by the software provider and decrypting the second encryption key using a private key to recover the first encryption key. The manufacturer then encrypts a program code using the recovered first encryption key and installs the seed in a certificate that is associated with the encrypted program code.

Abstract: A method for authenticating and deciphering an encrypted program file for execution by a secure element includes receiving the program file and a digital certificate that is associated with the program file from an external device. The method stores the program file and the associated certificate in a secure random access memory disposed in the secure element and hashes the program file to obtain a hash. The method authenticates the program file by comparing the obtained hash with a checksum that is stored in the certificate. Additionally, the method writes runtime configuration information stored in the certificate to corresponding configuration registers disposed in the secure element. The method further generates an encryption key using a seed value stored in the certificate and a unique identifier disposed in the secure element and deciphers the program file using the generated encryption key.

Abstract: A device includes a demodulator for receiving an encrypted content, an interface unit communicatively coupled to an external memory, and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received content. The hardware unit includes a processing unit, a ROM having a boot code causing the device to fetch data from the external memory, a RAM for storing the fetched data, multiple non-volatile memory registers or fuse banks, and a mechanism configured to write the stored data to an external storage device in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage device. The interface unit may include a wired or wireless communication link. The boot code includes executable instructions performing a series of validations. The device disables the executable instructions in the event of a validation failure.

Abstract: An integrated circuit includes a demodulator for receiving an encrypted message and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received message. The hardware unit includes a processing unit, a read-only access memory (ROM) having a boot code causing the integrated circuit to fetch data from an external memory, a random access memory (RAM) for storing the fetched data, multiple non-volatile memory registers or fuses, and an interface unit configured to write the data stored in the RAM to an external storage in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage. The interface unit may include a direct memory access controller. The external memory and the external storage can be a same non-volatile memory, namely a Flash device.

Abstract: An integrated circuit (IC) includes a demodulator for receiving encrypted information data and a hardware unit that enables conditional access to the information data. The hardware unit includes a processing unit, a RAM, a ROM, multiple non-volatile registers, and an interface unit for transferring an attribute to the demodulator. The non-volatile registers may include an IC identification and an encryption key. In an embodiment, the ROM includes a boot code that causes the processing unit to fetch a code from an external memory and store the fetched code in the RAM. The fetched code may include a certificate that ensures the authenticity of the code. The fetched code may be encrypted and decrypted by the ROM using the IC identification and the encryption key. The demodulator includes a descrambler for decrypting the received information data using the attribute. The information data may include digital radio or television content.

Abstract: A GNSS system operates intermittently and has adaptive activity and sleep time in order to reduce power consumption. The GNSS system provides an enhanced estimate of its position in the absence of GNSS signals of sufficient strength. The user's activity and behavior is modeled and used to improve performance, response time, and power consumption of the GNSS system. The user model is based, in part, on the received GNSS signals, a history of the user's positions, velocity, time, and inputs from other sensors disposed in the GNSS system, as well as data related to the network. During each activity time, the GNSS receiver performs either tracking, or acquisition followed by tracking. The GNSS receiver supports both normal acquisition as well as low-power acquisition.

Abstract: A GPS receiver includes an RF front end for acquiring and tracking a satellite signal and a baseband processor configured to preserve power. The baseband processor includes a GPS engine configured to process the satellite signal and generate a PVT fix, a power supervisory module for receiving the PVT fix, and a user state module that determines an environmental state, wherein the power supervisory module may power down the GPS receiver for a period of time based on a result of the determined environment state. The baseband processor also includes a time-based management module that adjusts the TCXO in response to the determined environmental state. The GPS receiver includes a plurality of operation modes, each of which is associated with a plurality of tracking profiles.

Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.

Abstract: System and method for providing clocks to digital circuitry with a need for multiple clocks. A preferred embodiment comprises an oscillator controller (oscillator clock domain block 305) distributes a system clock generated by an oscillator to a plurality of clock domain blocks (GSM clock domain block 310 and so forth). The clock domain blocks use the system clock to generate specific clocks needed by attached hardware. The clock domain blocks may be programmed after manufacture to permit customized clock generation to meet requirements.

Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.