Patents by Inventor Maximilian Rösch
Maximilian Rösch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136411Abstract: A transistor includes a semiconductor substrate having a first and second opposing major surfaces, a drain region of a first conductivity type at the second surface, a drift region of the first conductivity on the drain region, a body region of a second conductivity type that opposes the first conductivity type on the drift region, and a source region of a first conductivity type on and/or in the body region. A trench formed in the first surface has a base and sidewalls. A gate electrode in the trench is electrically insulated from the semiconductor substrate by a gate insulating layer. A field plate in the trench under the gate electrode is electrically insulated from the gate electrode and the semiconductor substrate by a field insulator. The base of the trench is positioned at a depth d from the first major surface, where 250 nm?d?800 nm.Type: ApplicationFiled: October 9, 2023Publication date: April 25, 2024Inventors: Seung Hwan Lee, Maximilian Rösch
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Patent number: 11908904Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.Type: GrantFiled: August 12, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies Austria AGInventors: Sylvain Leomant, Thomas Feil, Yulia Polak, Maximilian Roesch
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Publication number: 20230330581Abstract: A method and a filter device for the dry filtration of a gas flow carrying foreign objects in a filter device for purifying waste gas produced in additive manufacturing technologies, conducting a raw gas flow containing foreign objects into a raw gas space of a filter unit having at least one filter surface separating a raw gas side from a clean gas side, feeding oxidant to a reaction region located on the raw gas side of the filter surface downstream of the filter surface, such that foreign objects contained in material cleaned off from the filter surface and/or in the raw gas flow react with the oxidant in the reaction region to form foreign objects containing oxides.Type: ApplicationFiled: January 14, 2021Publication date: October 19, 2023Inventors: Walter Herding, Urs Herding, Sebastian Dandorfer, Stefan Hajek, Dino Bethke, Klaus Rabenstein, Maximilian Rösch, Thomas Sehr, Franz Weiss
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Patent number: 11699725Abstract: A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.Type: GrantFiled: December 11, 2020Date of Patent: July 11, 2023Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Oliver Blank, Franz Hirler, Maximilian Roesch, Li Juin Yip
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Patent number: 11682704Abstract: A method includes: forming a trench in a first major surface of a semiconductor substrate, the trench having a base and a side wall extending from the base to the first major surface; forming a first insulating layer on the trench base and side wall; forming a sacrificial layer on the first insulating layer on the trench side wall; forming a second insulation layer on the sacrificial layer; inserting conductive material into the trench that at least partially covers the second insulation layer; selectively removing portions of the second insulation layer uncovered by the conductive material; selectively removing the sacrificial layer to form a recess that is positioned adjacent the conductive material in the trench and that is bounded by the first insulation layer and the second insulating layer; and forming a third insulating layer in the trench that caps the recess to form an enclosed cavity in the trench.Type: GrantFiled: April 6, 2022Date of Patent: June 20, 2023Assignee: Infineon Technologies Austria AGInventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
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Publication number: 20230079987Abstract: A method for the dry filtration of a gas flow carrying foreign objects, a filter device for cleaning off waste gas resulting from additive manufacturing technologies, comprises feeding a raw gas flow containing foreign objects into a raw gas space of a filter unit having at least one filter surface separating a raw gas side from a clean gas side; feeding oxidant to a reaction region located on the raw gas side of the filter surface downstream of the filter surface; such that foreign objects contained in material cleaned off from the filter surface and/or in the raw gas flow react with the oxidant in the reaction region to form oxide-containing foreign objects.Type: ApplicationFiled: January 14, 2021Publication date: March 16, 2023Inventors: Walter Herding, Urs Herding, Sebastian Dandorfer, Stefan Hajek, Dino Bethke, Klaus Rabenstein, Maximilian Rösch, Thomas Sehr
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Publication number: 20230047420Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Sylvain Leomant, Thomas Feil, Yulia Polak, Maximilian Roesch
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Patent number: 11545545Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.Type: GrantFiled: July 16, 2020Date of Patent: January 3, 2023Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
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Publication number: 20220254892Abstract: The application relates to a semiconductor power device including a semiconductor body in which a transistor device is formed, the transistor device having a gate region and a channel region laterally aside the gate region, the gate region including a gate electrode for controlling a channel formation in the channel region, and a gate dielectric laterally between the channel region and the gate electrode. The gate electrode includes a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region. The gate electrode layer is made of a doped metallically conductive material.Type: ApplicationFiled: February 4, 2022Publication date: August 11, 2022Inventors: Jyotshna Bhandari, Gerald Patterer, Maximilian Roesch, Werner Schustereder, Stanislav Vitanov
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Publication number: 20220231136Abstract: A method includes: forming a trench in a first major surface of a semiconductor substrate, the trench having a base and a side wall extending from the base to the first major surface; forming a first insulating layer on the trench base and side wall; forming a sacrificial layer on the first insulating layer on the trench side wall; forming a second insulation layer on the sacrificial layer; inserting conductive material into the trench that at least partially covers the second insulation layer; selectively removing portions of the second insulation layer uncovered by the conductive material; selectively removing the sacrificial layer to form a recess that is positioned adjacent the conductive material in the trench and that is bounded by the first insulation layer and the second insulating layer; and forming a third insulating layer in the trench that caps the recess to form an enclosed cavity in the trench.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Inventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
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Patent number: 11316020Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending form the base to the first major surface, and a field plate arranged in the trench and an enclosed cavity in the trench. The enclosed cavity is defined by insulating material and is laterally positioned between a side wall of the field plate and the side wall of the trench.Type: GrantFiled: September 5, 2019Date of Patent: April 26, 2022Assignee: Infineon Technologies Austria AGInventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
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Publication number: 20210273067Abstract: A semiconductor device includes a contact opening extending through a source region and a body region of the device. An electrically insulative spacer lines sidewalls of the semiconductor substrate formed by the contact opening, and is recessed along the sidewalls such that at least part of the source region or body region is uncovered by the electrically insulative spacer. A body contact plug is in the contact opening. A first body contact region formed adjacent a bottom of the contact opening adjoins the body contact plug at the bottom of the contact opening. A second body contact region formed in the part of the source region or body region uncovered by the electrically insulative spacer adjoins the body contact plug along the part of the source region or body region uncovered by the electrically insulative spacer.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Wei-Chun Huang, Martin Poelzl, Thomas Feil, Maximilian Roesch
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Patent number: 11031478Abstract: A semiconductor device includes a trench extending into a first main surface of a semiconductor substrate, and a gate electrode and a gate dielectric in the trench. The gate dielectric separates the gate electrode from the semiconductor substrate. A first region having a first conductivity type is formed in the semiconductor substrate at the first surface adjacent the trench. A second region having a second conductivity type is formed in the semiconductor substrate below the first region adjacent the trench. A third region having the first conductivity type is formed in the semiconductor substrate below the second region adjacent the trench. A contact opening in the semiconductor substrate extends into the second region. An electrically insulative spacer is disposed on sidewalls of the semiconductor substrate formed by the contact opening, and an electrically conductive material in the contact opening adjoins the electrically insulative spacer on the sidewalls.Type: GrantFiled: January 23, 2018Date of Patent: June 8, 2021Assignee: Infineon Technologies Austria AGInventors: Wei-Chun Huang, Martin Poelzl, Thomas Feil, Maximilian Roesch
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Patent number: 11031466Abstract: A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.Type: GrantFiled: June 9, 2020Date of Patent: June 8, 2021Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.Inventors: Martin Poelzl, Robert Haase, Maximilian Roesch, Sylvain Leomant, Andreas Meiser, Bernhard Goller, Ravi Keshav Joshi
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Publication number: 20210098580Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.Type: ApplicationFiled: December 11, 2020Publication date: April 1, 2021Inventors: Martin Poelzl, Oliver Blank, Franz Hirler, Maximilian Roesch, Li Juin Yip
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Patent number: 10903321Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.Type: GrantFiled: October 13, 2015Date of Patent: January 26, 2021Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Oliver Blank, Franz Hirler, Maximilian Roesch, Li Juin Yip
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Patent number: 10868172Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate, the body region including a vertical channel region adjacent a sidewall of the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and by a portion of the body region; an electrically conductive material in the contact trench; and a diffusion barrier structure interposed between a sidewall of the contact trench and the vertical channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and configured to increase carrier mobility within the vertical channel region. Corresponding methods of manufacture are also described.Type: GrantFiled: December 18, 2019Date of Patent: December 15, 2020Assignee: Infineon Technologies Austria AGInventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
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Patent number: 10861966Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent a sidewall of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.Type: GrantFiled: December 18, 2019Date of Patent: December 8, 2020Assignee: Infineon Technologies Austria AGInventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
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Publication number: 20200350401Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.Type: ApplicationFiled: July 16, 2020Publication date: November 5, 2020Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
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Patent number: 10790353Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.Type: GrantFiled: November 9, 2018Date of Patent: September 29, 2020Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma