Patents by Inventor Maxwell Walthour Lippitt, III
Maxwell Walthour Lippitt, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8497565Abstract: In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115).Type: GrantFiled: March 8, 2011Date of Patent: July 30, 2013Assignee: Texas Instruments IncorporatedInventors: Byron Lovell Willaims, Maxwell Walthour Lippitt, III, Betty Mercer, Scott Montgomery, Binghua Hu
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Patent number: 8431463Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.Type: GrantFiled: August 10, 2009Date of Patent: April 30, 2013Assignee: Texas Instruments IncorporatedInventors: Maxwell Walthour Lippitt, III, Stephen Arlon Meisner, Lee Alan Stringer, Stephen Fredrick Clark, Fred Percy Debnam, II, Byron Lovell Williams
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Publication number: 20110156209Abstract: In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115).Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Byron Lovell Williams, Maxwell Walthour Lippitt, III, Betty Mercer, Scott Montgomery, Binghua Hu
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Patent number: 7902033Abstract: An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.Type: GrantFiled: February 12, 2008Date of Patent: March 8, 2011Assignee: Texas Instruments IncorporatedInventors: Byron Lovell Williams, Maxwell Walthour Lippitt, III, Betty Mercer, Scott Montgomery, Binghua Hu
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Patent number: 7800226Abstract: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.Type: GrantFiled: June 22, 2007Date of Patent: September 21, 2010Assignee: Agere Systems Inc.Inventors: Yuanning Chen, Maxwell Walthour Lippitt, III, William M. Moller
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Patent number: 7670920Abstract: An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.Type: GrantFiled: April 9, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Byron Lovell Williams, Maxwell Walthour Lippitt, III, C. Matthew Thompson
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Publication number: 20100032803Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Maxwell Walthour Lippitt, III, Stephen Arlon Meisner, Lee Alan Stringer, Stephen Fredrick Clark, Fred Percy Debnam, II, Byron Lovell Williams
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Publication number: 20090200637Abstract: An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.Type: ApplicationFiled: February 12, 2008Publication date: August 13, 2009Inventors: Byron Lovell Williams, Maxwell Walthour Lippitt, III, Betty Mercer, Scott Montgomery, Binghua Hu
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Patent number: 7250356Abstract: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.Type: GrantFiled: September 17, 2002Date of Patent: July 31, 2007Assignee: Agere Systems Inc.Inventors: Yuanning Chen, Maxwell Walthour Lippitt, III, William M. Moller