Abstract: An apparatus for storing data for read and write access receiving reset control signals, comprising a plurality of storage blocks, each block including an array of memory units for storing a unit of data is provided that is reset along storage block boundaries. A reset control means, coupled to receive the reset control signals which identify at least one of the storage blocks, is included for generating block reset signals. A means, coupled to the memory units in each storage block and to receive the block reset signals, for resetting the identified block of memory to 0. .

Abstract: The circuit provides one or several banks of capacitors, the capacitors in each bank being identical in size. A single fuse for each bank of capacitors controls the connection of the capacitors to a pulse-width-determining node on each of the ATD (address-transition-detect) pulse generators of the SRAM device. Depending on the position of the fuse in the circuit, the blowing of a single fuse can either add to the capacitance at the ATD nodes or substract from it. Thus the pulse-width of all ATD pulse generators can be adjusted shorter or longer simultaneously by blowing a single fuse only.