Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: In one embodiment, a semiconductor device includes substrate, a plurality of electrode layers provided above the substrate, and separated from each other in a first direction perpendicular to a surface of the substrate, and a first plug provided in the plurality of electrode layers. The device further includes first and second diffusion layers provided in the substrate, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit, a second plug provided at a position that overlaps with the first diffusion layer in planar view, and electrically connected with the first diffusion layer, and a third plug provided at a position that does not overlap with the first diffusion layer in planar view, and electrically connected with the first diffusion layer.

Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: According to an embodiment, a semiconductor storage device includes a first chip including a power supply protection circuit. The power supply protection circuit including: a resistor including a first end connected to the second pad; a first capacitor including a first end connected to a second end of the resistor; a first transistor including a first end connected to the second pad, a second end connected to a node with a signal of a value based on a voltage of the first end of the first capacitor, and a gate connected to the first pad; a first inverter including an input terminal connected to the second end of the first transistor; and a second transistor including a gate connected to an output terminal of the first inverter.

Abstract: According to an embodiment, a semiconductor storage device includes a first chip including a power supply protection circuit. The power supply protection circuit including: a resistor including a first end connected to the second pad; a first capacitor including a first end connected to a second end of the resistor; a first transistor including a first end connected to the second pad, a second end connected to a node with a signal of a value based on a voltage of the first end of the first capacitor, and a gate connected to the first pad; a first inverter including an input terminal connected to the second end of the first transistor; and a second transistor including a gate connected to an output terminal of the first inverter.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip; a first wiring and a second wiring which are provided above a first surface of the first semiconductor chip; a first terminal connected to one end of the first wiring and one end of the second wiring, and connected to an outside; a second terminal connected to the other end of the first wiring; and a third terminal connected to the other end of the second wiring, and connected to the second terminal.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip; a first wiring and a second wiring which are provided above a first surface of the first semiconductor chip; a first terminal connected to one end of the first wiring and one end of the second wiring, and connected to an outside; a second terminal connected to the other end of the first wiring; and a third terminal connected to the other end of the second wiring, and connected to the second terminal.

Abstract: According to one embodiment, a semiconductor device includes a first differential amplifier and a second differential amplifier. The first differential amplifier charges the first output terminal with a second voltage different from a first voltage. The first differential amplifier uses a first clock signal, stopping the charging at the first output terminal, receives first complementary data of the first voltage at the rising edge of a second clock signal, and outputs the first complementary data at the second voltage. The second differential amplifier charges the second output terminal with the second voltage. The second differential amplifier uses a third clock signal, stopping the charging at the second output terminal, receives second complementary data of the first voltage at the rising edge of a fourth clock signal, and outputs the second complementary data at the second voltage.

Abstract: According to one embodiment, a semiconductor device includes a first differential amplifier and a second differential amplifier. The first differential amplifier charges the first output terminal with a second voltage different from a first voltage. The first differential amplifier uses a first clock signal, stopping the charging at the first output terminal, receives first complementary data of the first voltage at the rising edge of a second clock signal, and outputs the first complementary data at the second voltage. The second differential amplifier charges the second output terminal with the second voltage. The second differential amplifier uses a third clock signal, stopping the charging at the second output terminal, receives second complementary data of the first voltage at the rising edge of a fourth clock signal, and outputs the second complementary data at the second voltage.