Patents by Inventor Maya Safieddine

Maya Safieddine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907634
    Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Gavin B. Meil, Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine
  • Publication number: 20230074528
    Abstract: A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 9, 2023
    Inventors: Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Stephen Gerard Shuma, Stephen John Barnfield, Maya Safieddine, Benedikt Geukes, Klaus-Dieter Schubert, Gabor Drasny
  • Publication number: 20230072459
    Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 9, 2023
    Inventors: Gavin B. Meil, Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine