Abstract: A peeling method includes a first decompression step, a pressure-heating step, and a second decompression step. In the first decompression step, an object with a skin to be peeled is placed in a pressure chamber being sealed, and an inside of the pressure chamber is decompressed to a predetermined first negative pressure state. In the pressure-heating step, the inside of the pressure chamber is pressure-heated to a predetermined pressure-heating state after the first decompression step. In the second decompression step, the inside of the pressure chamber is decompressed to a predetermined second negative pressure state after the pressure-heating step.

Abstract: A grain and flour supply apparatus is provided, including a holding bin provided above a container and having an exhaust port from which gas is discharged, an introduction port into which grain and flour are introduced, and a supply port which supplies the grain and flour to the container; a first vacuum breaker valve opening and closing the exhaust port; a second vacuum breaker valve opening and closing the introduction port; a third vacuum breaker valve opening and closing the supply port; a temperature sensor measuring the temperature in the holding bin; a vacuum device drawing a vacuum in the holding bin; and a control device configured to control the first vacuum breaker valve, the second vacuum breaker valve, the third vacuum breaker valve, and the vacuum device, and set with a target temperature.

Abstract: A granule preheating device, which preheats a granular food material stored at a low temperature to a predetermined preheating temperature suitable for processing before processing the granular food material with a food processing machine, includes: a housing that accommodates the granular food material, a stirring shaft that rotates a stirring blade to stir the granular food material in the housing, a microwave irradiation device that irradiates microwaves from above the granular food material in the housing, and a control device that controls at least the microwave irradiation device so as to preheat the granular food material being stirred by the stirring shaft until the temperature is uniformly increased to the predetermined preheating temperature of 25° C. or higher and 30° C. or lower suitable for processing within a predetermined preheating time of 10 minutes or less.

Abstract: A peeling method includes a first decompression step, a pressure-heating step, and a second decompression step. In the first decompression step, an object with a skin to be peeled is placed in a pressure chamber being sealed, and an inside of the pressure chamber is decompressed to a predetermined first negative pressure state. In the pressure-heating step, the inside of the pressure chamber is pressure-heated to a predetermined pressure-heating state after the first decompression step. In the second decompression step, the inside of the pressure chamber is decompressed to a predetermined second negative pressure state after the pressure-heating step.

Abstract: A grain and flour supply apparatus is provided, including a holding bin provided above a container and having an exhaust port from which gas is discharged, an introduction port into which grain and flour are introduced, and a supply port which supplies the grain and flour to the container; a first vacuum breaker valve opening and closing the exhaust port; a second vacuum breaker valve opening and closing the introduction port; a third vacuum breaker valve opening and closing the supply port; a temperature sensor measuring the temperature in the holding bin; a vacuum device drawing a vacuum in the holding bin; and a control device configured to control the first vacuum breaker valve, the second vacuum breaker valve, the third vacuum breaker valve, and the vacuum device, and set with a target temperature.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP1 and a polysilicon capacitor PIP2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor region HS1 constituting a lower electrode of the MOS capacitor MOS1 and a high-concentration semiconductor region HS2 constituting a lower electrode of the MOS capacitor MOS2 are coupled. Further, an electrode E1 constituting an upper electrode of the MOS capacitor MOS1 is coupled to the low potential (for example, GND) and an electrode E3 constituting an upper electrode of the MOS capacitor MOS2 is coupled to the high potential (for example, power source potential).

Abstract: A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP1 and a polysilicon capacitor PIP2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor region HS1 constituting a lower electrode of the MOS capacitor MOS1 and a high-concentration semiconductor region HS2 constituting a lower electrode of the MOS capacitor MOS2 are coupled. Further, an electrode E1 constituting an upper electrode of the MOS capacitor MOS1 is coupled to the low potential (for example, GND) and an electrode E3 constituting an upper electrode of the MOS capacitor MOS2 is coupled to the high potential (for example, power source potential).

Abstract: A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP1 and a polysilicon capacitor PIP2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor region HS1 constituting a lower electrode of the MOS capacitor MOS1 and a high-concentration semiconductor region HS2 constituting a lower electrode of the MOS capacitor MOS2 are coupled. Further, an electrode E1 constituting an upper electrode of the MOS capacitor MOS1 is coupled to the low potential (for example, GND) and an electrode E3 constituting an upper electrode of the MOS capacitor MOS2 is coupled to the high potential (for example, power source potential).