Patents by Inventor Mayan Moudgill

Mayan Moudgill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12165030
    Abstract: A system and method include an accelerator circuit comprising an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block and a processor to initialize the accelerator circuit, determining tasks of a neural network application to be performed by at least one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, assign each of the tasks to a corresponding one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, instruct the accelerator circuit to perform the tasks, and execute the neural network application based on results received from the accelerator circuit completing performance of the tasks.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: December 10, 2024
    Inventors: Mayan Moudgill, John Glossner
  • Patent number: 12050910
    Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store a trigonometric calculation instruction for evaluating a trigonometric function, and data registers comprising a first data register to store a floating-point input value associated with the trigonometric calculation instruction. The accelerator circuit further includes a determination circuit to identify the trigonometric calculation function and the floating-point input value associated with the trigonometric calculation instruction and determine whether the floating-point input value is in a small value range, and an approximation circuit to responsive to determining that the floating-point input value is in the small value, receive the floating-point input value and calculate an approximation of the trigonometric function with respect to the input value.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 30, 2024
    Inventors: Mayan Moudgill, Pablo Balzola, Murugappan Senthivelan, Vaidyanathan Ramdurai, Sitij Agrawal
  • Patent number: 11928465
    Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 12, 2024
    Inventors: Mayan Moudgill, Pablo Balzola, Murugappan Senthivelan, Vaidyanathan Ramdurai, Sitij Agrawal
  • Patent number: 11650817
    Abstract: A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 16, 2023
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, Murugappan Senthilvelan
  • Patent number: 11544214
    Abstract: A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: January 3, 2023
    Assignee: Optimum Semiconductor Technologies, Inc.
    Inventors: Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan, Pablo Balzola, Vitaly Kalashnikov, Sitij Agrawal
  • Patent number: 11157407
    Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 26, 2021
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, A. Joseph Hoane
  • Patent number: 11144815
    Abstract: A system includes a memory, a processor, and an accelerator circuit. The accelerator circuit includes an internal memory, an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block to concurrently perform tasks of a neural network application assigned to the accelerator circuit by the processor.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 12, 2021
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, John Glossner
  • Patent number: 10922267
    Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more graphics processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: February 16, 2021
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Vitaly Kalashnikov, Sitij Agrawal
  • Patent number: 10908909
    Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: February 2, 2021
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, Gary Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan
  • Patent number: 10846259
    Abstract: A computer processor is disclosed. The computer processor comprise a vector unit comprising a vector register file comprising at least one vector register to hold a varying number of elements. The computer processor further comprises out-of-order issue logic that holds a pool of vector instructions, selects a vector instruction from the pool, and sends the vector instruction for execution. The vector instruction operates on the varying number of elements of the at least one vector register.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: November 24, 2020
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan, Pablo Balzola
  • Patent number: 10824586
    Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 3, 2020
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Sitij Agrawal
  • Patent number: 10733140
    Abstract: A computer processor is disclosed. The computer processor may comprises a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that produce results with elements of widths different than that of the input elements. The computer processor may be implemented as a monolithic integrated circuit.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: August 4, 2020
    Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.
    Inventors: Mayan Moudgill, Arthur Joseph Hoane, Paul Hurtley
  • Patent number: 10719451
    Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 21, 2020
    Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.
    Inventors: Mayan Moudgill, A. Joseph Hoane, Lei Wang, Gary Nacer, Aaron G. Milbury, Enrique A. Barria, Paul Hurtley
  • Patent number: 10514915
    Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: December 24, 2019
    Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.
    Inventors: Mayan Moudgill, Gary Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan, Pablo Balzola
  • Patent number: 10339094
    Abstract: A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 2, 2019
    Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
    Inventors: Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan, Pablo Balzola, Vitaly Kalashnikov, Sitij Agrawal
  • Patent number: 10339095
    Abstract: A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor further comprises processing logic configured to operate on the varying number of elements in the vector register file using one or more digital signal processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 2, 2019
    Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.
    Inventors: Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan, Pablo Balzola, Vitaly Kalashnikov, Sitij Agrawal
  • Patent number: 10169039
    Abstract: A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 1, 2019
    Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
    Inventors: Mayan Moudgill, Gary Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan, Pablo Balzola
  • Publication number: 20180203703
    Abstract: A processor includes a plurality of physical registers and a processor core, communicatively coupled to the plurality of physical registers, the processor core to execute a process comprising a plurality of instructions to responsive to issuance of a call instruction for out-of-order execution, identify, based on a head pointer of the plurality of physical registers, a first physical register of the plurality of physical registers, store a return address in the first physical register, wherein the first physical register is associated with a first identifier, store, based on an out-of-order pointer of a call stack associated with the process, the first identifier in a first entry of the call stack, and increment, modulated by a length of the call stack, the out-of-order pointer of the call stack to point to a second entry of the call stack.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 19, 2018
    Inventors: Mayan Moudgill, Gary Nacer, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan
  • Publication number: 20180203806
    Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 19, 2018
    Inventors: Mayan Moudgill, A. Joseph Hoane, Lei Wang, Gary Nacer, Aaron G. Milbury, Enrique A. Barria, Paul Hurtley
  • Publication number: 20180173625
    Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 21, 2018
    Inventors: Mayan Moudgill, A. Joseph Hoane