Abstract: An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.

Abstract: A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue u

Abstract: A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the instruction decoder for processing integer type instructions, and a vector unit coupled to the instruction decoder for processing vector type instructions. A reduction unit is preferably associated with the vector unit and receives parallel data elements processed in the vector unit. The reduction unit generates a serial output from the parallel data elements. The processor may be configured to execute at least control code, digital signal processor (DSP) code, Java code and network processing code, and is therefore well-suited for use in a convergence device. The processor is preferably configured to utilize token triggered threading in conjunction with instruction pipelining.

Abstract: A method that allows a called procedure to determine a “safe” upper bound value representing the amount of data that can be written to a stack allocated array/buffer without overwriting any stack-defined data stored in reserved memory blocks in the stack (i.e., any region in memory that is preserved by a calling sequence). More specifically, when a called procedure is passed a stack allocated array/buffer as an argument, the method of the present invention allows the called procedure to call a “bounds checking” procedure that calculates and returns the “safe” upper bound value, thereby allowing the called procedure to prevent, e.g., potentially overwriting a procedure return value due to array overflow when writing data to the array. Advantageously, the “bounds checking” procedure may readily be implemented in any operating system/library to provide secure implementations of library functions that provide buffer overflow vulnerabilities.

Abstract: A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of control signals in a plurality of buffers proximate to a plurality of execution units, wherein the control signals are predecoded instructions of the second instruction set, executing an instruction of the first instruction set in response to a branch instruction of the first instruction set, and executing the control signals for an instruction of the second instruction set in response to a branch instruction of the second instruction set.

Abstract: A microprocessor includes a logic circuit. A selection device is coupled to the logic circuit, and the selection device provides switching of on/off states of the logic circuit based on a stored logical value. A program instruction is included which sets the stored logical value to control the on/off states of the logic circuit based on anticipated usage of the logical circuit in accordance with an instruction sequence of the microprocessor.

Abstract: A volatile memory device, in accordance with the present invention, includes an array of memory cells with at least two dummy cells disposed within the memory array. A driver is included for writing a first state to one of the at least two dummy cells and for writing a second state to another one of the at least two dummy cells. A comparison circuit compares the first state and the second state to a threshold to determine if a refresh of the array of memory cells is needed.

Abstract: The present invention features a computer with a mechanism for implementing precise interrupts for statically speculated instructions. One or more assumptions are generated, and all instructions in each assumption are tagged identically and statically scheduled on a speculative basis. An instruction is then modified or inserted at one or more decision points prior to the point at which the instruction was speculated. The decision points may be positive ones (the instructions scheduled under that assumption have succeeded) or negative ones (the instructions scheduled under that assumption have failed), or both. A decision point may be positive for one assumption and negative for another assumption. Static speculation may be performed down both sides of branches and may be performed simultaneously for multiple, independent paths. Efficient restart can also be effected.

Abstract: A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

Abstract: A computer processing system stores sequences of instructions in a memory for execution by a processor unit. An out-of-order load instruction may be created, either statically or dynamically, by moving a load instruction from its original position in a sequence of instructions to an earlier position in said sequence of instructions. Such out-of-order load instruction identifies a location in memory from which to read a datum and a first destination register in which to place the datum. The present invention is a method and corresponding apparatus that utilizes data comparison to detect coherence among memory and the datum read by an out-of-order load operation. More specifically, the method consists of an interference test which controls the processor unit to read a datum from the same location in memory identified by the out-of-order load instruction and compare the newly read datum with the datum saved in the first destination register.