Abstract: In an example, a circuit includes a transmitter path; a receiver path having an input to receive an input signal and an output to output a voltage signal; and high-pass filter circuitry having an input coupled to the output of the receiver path and having an output coupled to the input of the receiver path. The high-pass filter circuitry is configurable to receive a first control signal to cause a corner frequency of the high-pass filter circuitry to increase from a first value to a second value. The transmitter path is configurable to, simultaneously or after the corner frequency of the high-pass filter circuitry is increased to the second value, transmit a radar signal. During transmission of the radar signal in the transmitter path, the high-pass filter circuitry is configurable to receive a second control signal to cause the corner frequency to decrease from the second value.

Abstract: An example radar system includes a controller coupled to a transimpedance amplifier in a forward path of receiver circuitry and to variable resistance circuitry in a feedback path of the receiver circuitry. The variable resistance circuitry is coupled to an input of a high-pass filter in the feedback path. The controller is operable to increase transconductance of the transimpedance amplifier and decrease resistance provided by the variable resistance circuitry to the high-pass filter for a programmable duration for each chirp transmitted by the radar system. The programmable duration begins before the start of transmission of the corresponding chirp and ends during transmission of the corresponding chirp.

Abstract: An electronic device and method for machine learning (ML) based emotion and voice conversion in audio using virtual domain mixing and fake pair-masking is disclosed. The electronic device receives a source audio associated with a first user, a reference-speaker audio associated with a second user, and a reference-emotion audio associated with a third user. The electronic device applies a set of ML models to generate a converted audio. The generated converted audio is associated with content of the source audio, an identity of the second user and an emotion of the third user. The electronic device applies each of a source speaker classifier and a source emotion classifier on the converted audio, and re-trains an adversarial model. Based on the re-training, the adversarial model may allow conversion of an input audio to an output audio associated with the identity of the second user and the emotion of the third user.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a receiver path including a transimpedance amplifier having an output coupled to the ADC; and a controller coupled to the receiver path and configured to, upon detection of a jamming event of the receiver path, cause an increase in a transconductance of the transimpedance amplifier from a first transconductance value to a second transconductance value.

Abstract: In some implementations, a system may receive an authentication key associated with authenticating use of a generative AI model. The system may receive an input prompt. The system may generate, using the generative AI model, an output based on the input prompt. The authentication key is embedded within the output. A quality of the output is higher when the authentication key is valid than when the authentication key is not valid.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a transmitter path; a receiver path including a first amplifier including: an output coupled to the ADC, and a first high-pass filter; and a controller coupled to the transmitter path and to the receiver path, where the controller is configured to: cause a corner frequency of the first high-pass filter to increase from a first value to a second value, simultaneously or after causing the corner frequency of the first high-pass filter to increase, cause the transmitter path to be enabled, and after a first signal begins transmission in the enabled transmitter path, and during transmission of the first signal in the enabled transmitter path, cause the corner frequency of the first high-pass filter to decrease from the second value to the first value.

Abstract: In some implementations, a system may receive an authentication key associated with authenticating use of a generative AI model. The system may receive an input prompt. The system may generate, using the generative AI model, an output based on the input prompt. The authentication key is embedded within the output. A quality of the output is higher when the authentication key is valid than when the authentication key is not valid.

Abstract: Disclosed is a Phase-Locked Loop (PLL) with an improved ring oscillator 200. The Phase-Locked Loop (PLL) comprises a delay cell 100. The delay cell 100 may further comprise a main cell 102. Further a delay compensation circuitry 104, is integrally connected with the main cell 102. The Phase-Locked Loop (PLL) comprises a ring oscillator 200 connected with the delay circuit 100. Further the ring oscillator 200 is configured to be supply sensitive and assisted with a resistor. The ring oscillator 200 is connected to the delay cell 102 via the delay compensation circuitry 104. Further the ring oscillator 200 comprises a plurality of stages 202, and each stage from the plurality of stages 202 is cross-coupled with a next or an adjacent stage from the plurality of stages 202.

Abstract: A circuit for an edge-based Phase Frequency Detector (PFD) (200) comprising two edge detectors (103), two SR latches (104), one NAND gate (106), and one NOR gate (107). A reference (Ref) (101) and feedback signals (Fb) (102) are provided to the two edge detector (103) which generates a pulse of active low logic. The output of the edge detector (103) is provided to the two SR latches (104), which provide output signals of the phase frequency detectors. The output of two SR latch (104) is buffered though two invertors (201) and additionally connected to a pair of cross-coupled inverters (202) to generate complementary up (UP and UPb) and down (DN and DNb) signals (105). Phase Frequency Detector (PFD) circuit (200) minimize the number of gates, reducing noise and Random Jitter (RJ), enhance dead zone performance and also reduce the duty cycle of the reference (Ref) (101) and feedback (Fb) signal (102) to a minimal 10%.

Abstract: A quadrature generation circuit comprises a VCO's two-phase outputs (inp and inn) are buffered through two inverters that generate the output of low pass filtered signals (p and n). Further low pass filtered signals (p and n) output is given to an arbitrary delay, to generate four delayed signals (p1d, p2d, n1d, and n2d). Phase averaging of (p and n2d) as well as (n and p2d) is performed to generate the output of (I and Ib) clocks respectively. In the same way, p1d and n1d signals output are given to two investors to perform phase averaging which generates the output of the Q and Qb clocks. The output clocks (I, Ib, Q, and Qb) have a 90-degree phase shift with each other.

Abstract: The present invention discloses an electronic device having a multi-lobe differential inductor with two terminals fabricated on a P-substrate, The electronic device comprises a broken ring electrically coupled with the ground ring (M5), positioned around a perimeter of the substrate such that the inductor is surrounded by the ground ring and the broken ring. The broken ring defines a plurality of parallelly arranged structures; each structure comprises a plurality of metal segments (M1-M4, M6-M10) parallel to each other and electrically connected to and perpendicular to the ground ring.

Abstract: A circuit and a method for optimizing data frequency and power consumption has a circuit comprising a flip flop which comprises a plurality of latches interconnected. Each latch of the plurality of latches comprises a plurality of pairs of transistors comprising a first plurality of transistors. The at least one transistor of the first plurality of transistors is connected to ground and at least another transistor of the first plurality of transistors is connected to power supply. Further, each latch of the plurality of latches comprises a second plurality of transistors and a third plurality of transistors. The third plurality of transistors is configured between the first plurality of transistors and the second plurality of transistors. Further, each transistor of the third plurality of transistors is connected to at least one of a transistor of the first plurality of transistors or a transistor of the second plurality of transistors.

Abstract: Present disclosure relates to BGR circuit (100) and method (500) for generating BGR voltage. BGR circuit (100) comprises bandgap reference core circuit (102) and complementary-to-absolute-temperature (CTAT) generation circuit (104). Base of transistor (Q1) connected to ground and base of transistor (Q2) connected to VX. CTAT generation circuit (104) comprises second current mirror, third current mirror, third transistor (Q3), load resistor (RL), second resistor (R2) and third resistor (R3). Base of transistor Q2 connected to one end of resistor (R2) and one end of resistor (R3). Other end of resistor (R3) is connected to ground. Other end of second resistor (R2) is connected to emitter of transistor (Q3) and drain of third MOSFET (M3). Output of amplifier coupled to first current mirror and second current mirror. Second resistor (R2) connected to drain of M3 and CTAT generation circuit (104) has output node for outputting BGR voltage.

Abstract: An electronic device and method for iterative enhancement of speech recognition, voice conversion, and text-to-speech models are disclosed. The electronic device receives a text dataset and a dataset associated with a speech recognition task. Speech recognition, voice conversion, and TTS conversion models are trained for corresponding tasks. The device further iteratively executes operations, which include: generating an augmented speech dataset via application of the trained voice conversion model, finetuning the TTS conversion model using the augmented speech dataset, applying the finetuned TTS conversion model to the text dataset to generate speech samples, applying the trained voice conversion model to the speech samples to create an augmented text-speech dataset, finetuning the speech recognition model utilizing the augmented text-speech dataset, and finetuning the trained voice conversion model using the finetuned speech recognition model.

Abstract: In a radar system, an intermediate frequency amplifier (IFA) is configured with two high-pass filter stages, each having an amplifier and a configurable impedance component. A control signal is activated as the radar system begins to transmit a chirp signal to lower the impedance of the configurable impedance components during an initial portion of the chirp transmission to achieve faster settling of the IFA output signal. After the initial portion, the control signal deactivates while transmission of the chirp continues to increase the impedance of the configurable impedance components to a level sufficient to effectively perform filtering of unwanted signals received by the radar system.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a transmitter path; a receiver path including a first amplifier including: an output coupled to the ADC, and a first high-pass filter; and a controller coupled to the transmitter path and to the receiver path, where the controller is configured to: cause a corner frequency of the first high-pass filter to increase from a first value to a second value, simultaneously or after causing the corner frequency of the first high-pass filter to increase, cause the transmitter path to be enabled, and after a first signal begins transmission in the enabled transmitter path, and during transmission of the first signal in the enabled transmitter path, cause the corner frequency of the first high-pass filter to decrease from the second value to the first value.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a receiver path including a transimpedance amplifier having an output coupled to the ADC; and a controller coupled to the receiver path and configured to, upon detection of a jamming event of the receiver path, cause an increase in a transconductance of the transimpedance amplifier from a first transconductance value to a second transconductance value.

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Abstract: An electronic device and method for machine learning (ML) based emotion and voice conversion in audio using virtual domain mixing and fake pair-masking is disclosed. The electronic device receives a source audio associated with a first user, a reference-speaker audio associated with a second user, and a reference-emotion audio associated with a third user. The electronic device applies a set of ML models to generate a converted audio. The generated converted audio is associated with content of the source audio, an identity of the second user and an emotion of the third user. The electronic device applies each of a source speaker classifier and a source emotion classifier on the converted audio, and re-trains an adversarial model. Based on the re-training, the adversarial model may allow conversion of an input audio to an output audio associated with the identity of the second user and the emotion of the third user.

Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.