Abstract: A circuit and a method for optimizing data frequency and power consumption has a circuit comprising a flip flop which comprises a plurality of latches interconnected. Each latch of the plurality of latches comprises a plurality of pairs of transistors comprising a first plurality of transistors. The at least one transistor of the first plurality of transistors is connected to ground and at least another transistor of the first plurality of transistors is connected to power supply. Further, each latch of the plurality of latches comprises a second plurality of transistors and a third plurality of transistors. The third plurality of transistors is configured between the first plurality of transistors and the second plurality of transistors. Further, each transistor of the third plurality of transistors is connected to at least one of a transistor of the first plurality of transistors or a transistor of the second plurality of transistors.

Abstract: Present disclosure relates to BGR circuit (100) and method (500) for generating BGR voltage. BGR circuit (100) comprises bandgap reference core circuit (102) and complementary-to-absolute-temperature (CTAT) generation circuit (104). Base of transistor (Q1) connected to ground and base of transistor (Q2) connected to VX. CTAT generation circuit (104) comprises second current mirror, third current mirror, third transistor (Q3), load resistor (RL), second resistor (R2) and third resistor (R3). Base of transistor Q2 connected to one end of resistor (R2) and one end of resistor (R3). Other end of resistor (R3) is connected to ground. Other end of second resistor (R2) is connected to emitter of transistor (Q3) and drain of third MOSFET (M3). Output of amplifier coupled to first current mirror and second current mirror. Second resistor (R2) connected to drain of M3 and CTAT generation circuit (104) has output node for outputting BGR voltage.

Abstract: In a radar system, an intermediate frequency amplifier (IFA) is configured with two high-pass filter stages, each having an amplifier and a configurable impedance component. A control signal is activated as the radar system begins to transmit a chirp signal to lower the impedance of the configurable impedance components during an initial portion of the chirp transmission to achieve faster settling of the IFA output signal. After the initial portion, the control signal deactivates while transmission of the chirp continues to increase the impedance of the configurable impedance components to a level sufficient to effectively perform filtering of unwanted signals received by the radar system.

Abstract: An electronic device and method for iterative enhancement of speech recognition, voice conversion, and text-to-speech models are disclosed. The electronic device receives a text dataset and a dataset associated with a speech recognition task. Speech recognition, voice conversion, and TTS conversion models are trained for corresponding tasks. The device further iteratively executes operations, which include: generating an augmented speech dataset via application of the trained voice conversion model, finetuning the TTS conversion model using the augmented speech dataset, applying the finetuned TTS conversion model to the text dataset to generate speech samples, applying the trained voice conversion model to the speech samples to create an augmented text-speech dataset, finetuning the speech recognition model utilizing the augmented text-speech dataset, and finetuning the trained voice conversion model using the finetuned speech recognition model.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a transmitter path; a receiver path including a first amplifier including: an output coupled to the ADC, and a first high-pass filter; and a controller coupled to the transmitter path and to the receiver path, where the controller is configured to: cause a corner frequency of the first high-pass filter to increase from a first value to a second value, simultaneously or after causing the corner frequency of the first high-pass filter to increase, cause the transmitter path to be enabled, and after a first signal begins transmission in the enabled transmitter path, and during transmission of the first signal in the enabled transmitter path, cause the corner frequency of the first high-pass filter to decrease from the second value to the first value.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a receiver path including a transimpedance amplifier having an output coupled to the ADC; and a controller coupled to the receiver path and configured to, upon detection of a jamming event of the receiver path, cause an increase in a transconductance of the transimpedance amplifier from a first transconductance value to a second transconductance value.

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Abstract: An electronic device and method for machine learning (ML) based emotion and voice conversion in audio using virtual domain mixing and fake pair-masking is disclosed. The electronic device receives a source audio associated with a first user, a reference-speaker audio associated with a second user, and a reference-emotion audio associated with a third user. The electronic device applies a set of ML models to generate a converted audio. The generated converted audio is associated with content of the source audio, an identity of the second user and an emotion of the third user. The electronic device applies each of a source speaker classifier and a source emotion classifier on the converted audio, and re-trains an adversarial model. Based on the re-training, the adversarial model may allow conversion of an input audio to an output audio associated with the identity of the second user and the emotion of the third user.

Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

Abstract: [Problem] To provide an autism treatment support system, an autism treatment support device, and a program capable of improving visual concentration of an autistic patient. [Means for solving] This technology relates to an autism treatment support system, an autism treatment support apparatus, and a program. An autism treatment support system includes a tracking unit for tracking a user's eye movement of a display unit of an autism treatment support apparatus, and an analysis unit for analyzing a tendency of the user's eye to move with respect to a gaze of the user with respect to the display unit. A determination unit includes a determination unit that determines a training content based on a tendency of movement of the eye of the user and a skill to be learned by the user determined based on a tendency of movement of the eye of the user, and an execution unit that executes a training program reflecting the determined training content on the autism treatment support apparatus.

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract: An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system.