Patents by Inventor Mayankkumar Hareshbhai Niranjani

Mayankkumar Hareshbhai Niranjani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230168699
    Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
    Type: Application
    Filed: October 17, 2022
    Publication date: June 1, 2023
    Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
  • Publication number: 20230168300
    Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.
    Type: Application
    Filed: November 8, 2022
    Publication date: June 1, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Mauro GIACOMINI, Fabio Enrico Carlo DISEGNI, Rajesh NARWAL, Pravesh Kumar SAINI, Mayankkumar HARESHBHAI NIRANJANI
  • Patent number: 11550348
    Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Gourav Garg
  • Patent number: 11513544
    Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 29, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
  • Publication number: 20220308610
    Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Gourav Garg