Patents by Inventor Mayk Roehrich
Mayk Roehrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10410980Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.Type: GrantFiled: December 14, 2017Date of Patent: September 10, 2019Assignee: Infineon Technologies AGInventors: Thomas Kuenemund, Mayk Roehrich
-
Patent number: 10110230Abstract: In various embodiments, a level shifter and a method for operating the same are provided. The level shifter may include a low supply voltage terminal, a high supply voltage terminal, at least one input terminal, at least one output terminal, and a latch. The latch may configured to: store a predetermined logic state by setting a storage node to a voltage level in response to receiving a predetermined voltage level at the at least one input terminal; amend the voltage level at the storage node in response to receiving an amended voltage/s at the low supply voltage terminal and/or at the high supply voltage terminal; and output the predetermined logic state having the amended voltage level from the storage node to the at least one output.Type: GrantFiled: August 15, 2017Date of Patent: October 23, 2018Assignee: Infineon Technologies AGInventors: Christoph Bukethal, Mayk Roehrich
-
Publication number: 20180174985Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.Type: ApplicationFiled: December 14, 2017Publication date: June 21, 2018Inventors: Thomas Kuenemund, Mayk Roehrich
-
Publication number: 20180062657Abstract: In various embodiments, a level shifter is provide. The level shifter includes a low supply voltage terminal, a high supply voltage terminal, at least one input terminal, at least one output terminal, and a latch. The latch is configured: to store a predetermined logic state by setting a storage node to a voltage level in response to receiving a predetermined voltage level at the at least one input terminal; to amend the voltage level at the storage node in response to receiving an amended voltage/s at the low supply voltage terminal and/or at the high supply voltage terminal; and to output the predetermined logic state having the amended voltage level from the storage node to the at least one output.Type: ApplicationFiled: August 15, 2017Publication date: March 1, 2018Inventors: Christoph Bukethal, Mayk Roehrich
-
Patent number: 9559108Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.Type: GrantFiled: May 22, 2015Date of Patent: January 31, 2017Assignee: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
-
Publication number: 20160211250Abstract: According to various embodiments, a semiconductor substrate arrangement may be provided, wherein the semiconductor substrate arrangement may include: a semiconductor substrate defining a first area at a first level and a second area next to the first area at a second level, wherein the first level is lower than the second level; a plurality of planar non-volatile memory structures disposed over the semiconductor substrate in the first area; and a plurality of planar transistor structures disposed over the semiconductor substrate in the second area.Type: ApplicationFiled: January 15, 2015Publication date: July 21, 2016Inventors: Wolfram LANGHEINRICH, Robert STRENZ, Georg TEMPEL, Knut STAHRENBERG, Nikolaos HATZOPOULOS, Christoph BUKETHAL, Klaus KNOBLOCH, Achim GRATZ, Mayk ROEHRICH
-
Publication number: 20150255477Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.Type: ApplicationFiled: May 22, 2015Publication date: September 10, 2015Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
-
Patent number: 9040375Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.Type: GrantFiled: January 28, 2013Date of Patent: May 26, 2015Assignee: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
-
Patent number: 9030877Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.Type: GrantFiled: October 11, 2012Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Robert Strenz, Wolfram Langheinrich, Mayk Roehrich, Robert Wiesner
-
Publication number: 20140213049Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
-
Patent number: 8320191Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.Type: GrantFiled: March 14, 2008Date of Patent: November 27, 2012Assignee: Infineon Technologies AGInventors: Robert Strenz, Wolfram Langheinrich, Mayk Roehrich, Robert Wiesner
-
Patent number: 7974114Abstract: In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line.Type: GrantFiled: April 28, 2009Date of Patent: July 5, 2011Assignee: Infineon Technologies AGInventors: Thomas Nirschl, Michael Bollu, Mayk Roehrich
-
Publication number: 20100271855Abstract: In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas Nirschl, Michael Bollu, Mayk Roehrich
-
Patent number: 7723777Abstract: One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.Type: GrantFiled: August 12, 2008Date of Patent: May 25, 2010Assignee: Infineon Technologies AGInventors: John Power, Mayk Roehrich, Martin Stiftinger, Robert Strenz
-
Publication number: 20100038696Abstract: One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: John POWER, Mayk ROEHRICH, Martin STIFTINGER, Robert STRENZ
-
Publication number: 20090059678Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.Type: ApplicationFiled: March 14, 2008Publication date: March 5, 2009Inventors: Robert Strenz, Wolfram Langheinrich, Mayk Roehrich, Robert Wiesner
-
Patent number: 7485542Abstract: A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.Type: GrantFiled: July 29, 2005Date of Patent: February 3, 2009Assignee: Infineon Technologies AGInventors: Achim Gratz, Mayk Roehrich, Veronika Polei
-
Patent number: 7342448Abstract: A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors.Type: GrantFiled: June 29, 2006Date of Patent: March 11, 2008Assignee: Infineon Technologies AGInventors: Benno Muhlbacher, Joachim Gratz, Evelyne Kricki, Thomas Pötscher, Mayk Roehrich, David San Segundo Bello, Andreas Weisbauer
-
Patent number: 7317631Abstract: A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.Type: GrantFiled: August 26, 2005Date of Patent: January 8, 2008Assignee: Infineon Technologies AGInventors: Achim Gratz, Mayk Roehrich, Klaus Knobloch
-
Patent number: 7212438Abstract: The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each floating gate transistor comprises a floating gate. Programming means coupled to the first and second floating gate transistor are operable to place a selected electrical charge in one of the floating gates and less than the selected electrical charge in the other floating gate to represent either a first or second binary value.Type: GrantFiled: February 25, 2005Date of Patent: May 1, 2007Assignee: Infineon Technologies AGInventors: Achim Gratz, Mayk Röhrich