Abstract: A pulse code multiplex exchange system includes a buffer arrangement for compensating both short and long term phase drift of information between plesiochronous data paths each being controlled for block information transfer by a separate clock. An alignment buffer is arranged between the two data paths. It has two sections, each having a capacity for storing alternately one of two subsequent information blocks, and on chip address decoders for selecting write and read addresses. Separate address generators are associated with the buffer for generating consecutive write addresses under control of a first clock and read addresses under control of a second clock, respectively. A guard distance detector continuously monitors the distance between the present write address and the respective read address, and initiates a slip operation for switching subsequent read operations from one section of the alignment buffer to the other section, if the address distance falls short of a minimal guard distance.