Abstract: A display device, which includes a lower face film, a TFT layer, and a light emitting element layer, includes a resin layer provided above the lower face film and below the TFT layer. A first region and a second region are included in a lower face of the resin layer, and the second region is a carbide pattern in which an amount of carbide per unit area is greater than an amount of carbide per unit area in the first region.

Abstract: A liquid crystal display device according to one aspect of the disclosure includes: a liquid crystal panel including a first substrate and a second substrate that oppose each other, and a liquid crystal layer of a horizontal alignment type provided between the first substrate and the second substrate; and a first polarizing plate and a second polarizing plate that sandwich the liquid crystal panel. A transparent conductive film layer connected to a ground potential is formed on the first substrate. A plurality of pixel electrodes are formed above the second substrate. A distance between the liquid crystal layer and the transparent conductive film layer ranges 15 ?m to 200 ?m.

Abstract: A liquid crystal display device according to an aspect of the disclosure includes a liquid crystal panel including an element substrate, a counter substrate facing the element substrate, a liquid crystal layer sandwiched between the element substrate and the counter substrate, an incident-side linear polarizing plate arranged on a light-incident side of the liquid crystal layer, and an emission-side linear polarizing plate arranged on a light-emission side of the liquid crystal layer. Each of the element substrate and the counter substrate uses a resin film as base material. A plurality of insulating films are formed on the base material. A contact hole is formed in the plurality of insulating films, the contact hole being rectangular in plan view. Either a long side or a short side of the contact hole is parallel with an absorption axis of the incident-side linear polarizing plate or the emission-side linear polarizing plate.

Abstract: A liquid crystal display device includes a first circuit board, a second circuit board, a liquid crystal layer, a light transmitting display area, a memory circuit, a liquid crystal driving voltage applying circuit, and a potential applying trace. The first circuit board includes a light reflecting electrode. The second circuit board includes a common electrode. The light transmitting display area is for transmitting light from an outer side of the first circuit board through the first circuit board. The memory circuit stores data based on a potential at a data signal trace. The liquid crystal driving voltage applying circuit is for adjusting a potential at the light reflecting electrode based on the data stored in the memory circuit. The potential applying trace includes an overlapping portion overlapping the light transmitting display area between the glass substrate and the first insulating film and is electrically connected to the memory circuit.

Abstract: Provided is a liquid crystal display device performing reflection display, wherein light leakage in areas where structural members are provided in a liquid crystal layer, and flicker during low frequency driving, are suppressed. The liquid crystal display device includes: a first substrate 11; a reflection electrode 14 provided on the first substrate 11, for each pixel; a second substrate 20 provided so as to be opposed to the first substrate 11; a liquid crystal layer 16 provided between the first substrate 11 and the second substrate 20; and a structural member 17 provided in the liquid crystal layer 16 in such a manner that the structural member 17 protrudes from one of the first substrate 11 and the second substrate 20 toward the other substrate. In an area of each pixel, no reflection electrode 14 is provided in an area where the structural member 17 is provided.

Abstract: A liquid crystal display device wherein a first substrate and a second substrate are bonded together by a sealing material, a pixel electrode, a common electrode, a shift register, a clock line, and a power supply line are formed on the first substrate, a plurality of conductive particles are mixed into the sealing material, the plurality of conductive particles are maintained at a same potential as the common electrode, and the plurality of conductive particles are disposed at a position overlapping at least a part of the power supply line, when viewed from a normal direction of the first substrate.

Abstract: A liquid crystal display device wherein a first substrate and a second substrate are bonded together by a sealing material, a pixel electrode, a common electrode, a shift register, a clock line, and a power supply line are formed on the first substrate, a plurality of conductive particles are mixed into the sealing material, the plurality of conductive particles are maintained at a same potential as the common electrode, and the plurality of conductive particles are disposed at a position overlapping at least a part of the power supply line, when viewed from a normal direction of the first substrate.

Abstract: In order to supply a low-level potential VSS from a trunk line for the low-level potential VSS to each stage of a shift register, a branch line and an auxiliary line are provided for every plurality of stages of the shift register, and the auxiliary lines are connected to the respective branch lines and the plurality of stages of the shift register. It is also possible to provide an auxiliary line having substantially the same length as the trunk line and to connect all of the branch lines and all of the stages in the shift register to this auxiliary line. A high-level potential VDD may also be supplied using the same method. Consequently, a scanning-signal-line driving circuit is provided in which the frame area and power consumption of a display panel can be reduced when formed on the display panel as an integral unit.

Abstract: A display device includes a monolithic gate driver with drive signal trunk wiring lines that transmit drive signals (such as clock signals) made of a source metal in a region on the opposite side of a display region with respect to a shift register region. A VSS trunk wiring line arranged to transmit a low-level direct-current power supply potential is made of a source metal in a region between the shift register region and the display region. Each of bistable circuits defining a shift register and a drive signal trunk wiring line are connected by a drive signal branch wiring line made of a gate metal. Each bistable circuit and the VSS trunk wiring line are connected by a VSS branch wiring line made of a source metal.

Abstract: A gate driver is provided with an odd-numbered stage shift register, an even-numbered stage shift register, and main lines including clock signal main lines. In at least one example embodiment, each stage of one of the shift registers receives the first clock and the second clock from the clock signal main lines, and the third clock and the fourth clock from an adjacently provided stage of the other shift register. Each stage of the shift register can receive the second clock from a different stage of the same shift register. With this, it is possible to reduce a picture-frame area of a panel in a display device provided with a scanning signal line drive circuit having the plurality of shift registers.

Abstract: A display device as an electronic apparatus in accordance with the present invention includes a clock signal wiring (104) for connecting to a source driver circuit; a power supply wiring (105) formed at a position where the power supply wiring (105) does not overlap with a projection plane of the clock signal wiring (104), so as to sandwich at least an insulating layer with a layer in which the clock signal wiring (104) is formed; and a capacitive electrode (109) electrically connected to the clock signal wiring (104). The capacitive electrode (109) is formed so as to overlap at least partially with a projection plane of the power supply wiring (105). A capacitance (301) is formed between the capacitive electrode (109) and the power supply wiring (105).

Abstract: Disclosed is a signal distribution device which is provided with: supply lines (5) for supplying input signals to switching elements in signal distribution circuits; and distribution lines (6) for distributing the input signals to output terminals via the switching elements. The corresponding one of the supply lines (5) and at least one of the distribution lines (6) each have an extension section (5a) and an extension section (5b) which extend in an extending direction of a control line (13). A selection signal for switching on/off the associated switching element is applied to the control line (13). The extension sections (5a and 5b) are formed at positions that do not overlap the edge portions of the control line (13) in the extending direction thereof.

Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.

Abstract: A peripheral region of a display panel includes a signal distribution device (4) for time-dividing and distributing, to output terminals (7), an output signal from a source driver. The signal distribution device (4) includes switching elements (20) for the output terminals (7). Each switching element (20) is controlled by a selection signal supplied to a control line (9) connected with a gate electrode. Each switching element (20) includes a source electrode and the drain electrode each having a comb-like shape having a stem part and branch parts extending therefrom. In at least one switching element (20), only all of or part of the branch parts overlap the control line (9) and a semiconductor layer (10). This suppresses abnormal heat generation of a source driver in a display device including the signal distribution circuit by which an output signal from the source driver is distributed to pixels in time series.

Abstract: A display device of at least one embodiment of the present invention has a connection changeover circuit, including switch elements for time-division driving, formed on a liquid crystal panel, and the switch elements are paired so that two switch elements in each pair are connected in parallel to one video signal line. The paired switch elements are turned on at the same time, and immediately before one of the switch elements is turned off upon completion of a charging period for its corresponding video signal line, only the other switch element is turned off. As a result, while maintaining drive performance, it is possible to solve the impact of fieldthrough phenomenon caused by one of the switch elements, which are transistors, and also reduce parasitic capacitance formed in the other switch element, thereby suppress the impact of fieldthrough phenomenon caused by that switch element.

Abstract: There is realized a scanning signal line drive circuit (in a display device) capable of, even in a case where a circuit in a shift register is formed using a thin-film transistor which is relatively large in off leakage, suppressing unnecessary power consumption due to a leakage current in the thin-film transistor. In at least one embodiment, bistable circuit that forms the shift register includes a thin-film transistor for raising a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin-film transistor, another thin-film transistor for lowering a potential of the region netA, and a region netB connected to a gate terminal of the other thin-film transistor. With this configuration, the potential of the region netB is raised based on a third clock which is advanced in phase by 90 degrees with respect to the first clock and is lowered based on a fourth clock which is delayed in phase by 90 degrees with respect to the first clock.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: Disclosed is a signal distribution device which is provided with: supply lines (5) for supplying input signals to switching elements in signal distribution circuits; and distribution lines (6) for distributing the input signals to output terminals via the switching elements. The corresponding one of the supply lines (5) and at least one of the distribution lines (6) each have an extension section (5a) and an extension section (5b) which extend in an extending direction of a control line (13). A selection signal for switching on/off the associated switching element is applied to the control line (13). The extension sections (5a and 5b) are formed at positions that do not overlap the edge portions of the control line (13) in the extending direction thereof.

Abstract: In a display device including a monolithic gate driver, without degrading display quality, miniaturization is achieved while reducing power consumption. Drive signal trunk wiring lines (71) that transmit drive signals such as clock signals are formed from a source metal (701) in a region on the opposite side of a display region with respect to a shift register region. A VSS trunk wiring line (73) for transmitting a low-level direct-current power supply potential is formed from a source metal (701) in a region between the shift register region and the display region. Each of bistable circuits forming a shift register (410) and a drive signal trunk wiring line (71) are connected by a drive signal branch wiring line (72) formed from a gate metal (702). Each bistable circuit and the VSS trunk wiring line (73) are connected by a VSS branch wiring line (74) formed from a source metal (701).