Abstract: A position measurement apparatus includes a reference value acquisition unit that obtains a plurality of reference geomagnetism information pieces, the plurality of reference geomagnetism information pieces being geomagnetism information pieces measured at a plurality of reference positions, an association information generation unit that generates association information that associates the plurality of reference positions with the plurality of reference geomagnetism information pieces, a measurement value acquisition unit that obtains measurement geomagnetism information, the measurement geomagnetism information being geomagnetism information measured at a measurement position and a position specifying unit that specifies a position corresponding to the measurement geomagnetism information based on association between the plurality of reference positions and the plurality of reference geomagnetism information pieces obtained by the association information.

Abstract: The present invention is directed to a semiconductor integrated circuit automatic lay-out method using a cell group constituted of a core cell in which a transistor and/or a logic gate are arranged and a wiring cell through which a power line and an inter-cell signal line between the core cells pass, comprising the steps of using the core cell and the wiring cell in an environment in which the number of grids for the inter-cell signal line is arbitrarily set in initial setting for automatic lay-out; detecting the number of the inter-cell signal lines which pass through the wiring cell of data obtained through cell arrangement and wiring processing; comparing the detected number of the inter-cell signal lines to the number of the initially set grids; and if the number of the grids is excessive or insufficient, replacing an initially set wiring cell with a wiring cell having the detected number of inter-cell signal lines.

Abstract: The present invention is directed to a semiconductor integrated circuit automatic lay-out method using a cell group constituted of a core cell in which a transistor and/or a logic gate are arranged and a wiring cell through which a power line and an inter-cell signal line between the core cells pass, comprising the steps of using the core cell and the wiring cell in an environment in which the number of grids for the inter-cell signal line is arbitrarily set in initial setting for automatic layout; detecting-the number of the inter-cell signal lines which pass through the wiring cell of data obtained through cell arrangement- and wiring processing; comparing the detected number of the inter-cell signal lines to the number of the initially set grids; and if the number of the grids is excessive or insufficient, replacing an initially set wiring cell with a wiring cell having the detected number of inter-cell signal lines.