Abstract: A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.

Abstract: A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating state to the second operating state, and based on the generated time-based waveform, identifying one or more operating state changes corresponding to the operating state analysis and associated timing window and cell information. The method includes verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints for generating an analysis report.