Patents by Inventor Mayur G. Kulkarni
Mayur G. Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11512391Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.Type: GrantFiled: June 25, 2020Date of Patent: November 29, 2022Assignee: Applied Materials, Inc.Inventors: Kalyanjit Ghosh, Mayur G. Kulkarni, Sanjeev Baluja, Kien N. Chuc, Sungjin Kim, Yanjie Wang
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Patent number: 11508611Abstract: Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110° to about 140° with respect to a longitudinal axis of the lift pin.Type: GrantFiled: October 25, 2019Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Kalyanjit Ghosh, Mayur G. Kulkarni, Sanjeev Baluja, Praket P. Jha, Krishna Nittala
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Publication number: 20200325577Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Kalyanjit GHOSH, Mayur G. KULKARNI, Sanjeev BALUJA, Kien N. CHUC, Sungjin KIM, Yanjie WANG
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Patent number: 10724138Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.Type: GrantFiled: May 30, 2018Date of Patent: July 28, 2020Assignee: Applied Materials, Inc.Inventors: Kalyanjit Ghosh, Mayur G. Kulkarni, Sanjeev Baluja, Kien N. Chuc, Sungjin Kim, Yanjie Wang
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Patent number: 10612135Abstract: Embodiments disclosed herein generally relate to systems and methods to prevent free radical damage to sensitive components in a process chamber and optimizing flow profiles. The processing chamber utilizes a cover substrate on lift pins and an inert bottom purge flow to shield the substrate support from halogen reactants. During a clean process, the cover substrate and the purge flow restricts halogen reactants from contacting the substrate support. The method of cleaning includes placing a cover substrate on a plurality of lift pins that extend through a substrate support in a processing chamber, raising the cover substrate via the lift pins to expose a space between the cover substrate and the substrate support, supplying a halogen containing gas into the processing chamber, supplying a second gas through an opening in the processing chamber, and flowing the second gas through the space between the cover substrate and the substrate support.Type: GrantFiled: July 19, 2017Date of Patent: April 7, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Sanjeev Baluja, Kalyanjit Ghosh, Ren-Guan Duan, Mayur G. Kulkarni, Gregory Siu, Praket P. Jha, Deenesh Padhi, Lei Guo, Wei Min Chan, Ajit Balakrishna
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Patent number: 10600624Abstract: Systems and methods for depositing a film in a PECVD chamber while reducing residue buildup in the chamber. In some embodiments disclosed herein, a processing chamber includes a chamber body, a substrate support, a showerhead, and one or more heaters configured to heat the showerhead. In some embodiments, the processing chamber includes a controller.Type: GrantFiled: December 21, 2018Date of Patent: March 24, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Kalyanjit Ghosh, Sanjeev Baluja, Mayur G. Kulkarni, Shailendra Srivastava, Tejas Ulavi, Yusheng Alvin Zhou, Amit Kumar Bansal, Priyanka Dash, Zhijun Jiang, Ganesh Balasubramanian, Qiang Ma, Kaushik Alayavalli, Yuxing Zhang, Daniel Hwung, Shawyon Jafari
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Publication number: 20200058538Abstract: Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110° to about 140° with respect to a longitudinal axis of the lift pin.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Kalyanjit GHOSH, Mayur G. KULKARNI, Sanjeev BALUJA, Praket P. JHA, Krishna NITTALA
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Patent number: 10490436Abstract: Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110° to about 140° with respect to a longitudinal axis of the lift pin.Type: GrantFiled: October 25, 2016Date of Patent: November 26, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Kalyanjit Ghosh, Mayur G. Kulkarni, Sanjeev Baluja, Praket P. Jha, Krishna Nittala
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Patent number: 10483282Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.Type: GrantFiled: February 4, 2019Date of Patent: November 19, 2019Assignee: Applied Materials, Inc.Inventors: Michael Wenyoung Tsiang, Praket P. Jha, Xinhai Han, Bok Hoen Kim, Sang Hyuk Kim, Myung Hun Ju, Hyung Jin Park, Ryeun Kwan Kim, Jin Chul Son, Saiprasanna Gnanavelu, Mayur G. Kulkarni, Sanjeev Baluja, Majid K. Shahreza, Jason K. Foster
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Publication number: 20190311887Abstract: The present disclosure relates to a fluid delivery system assembly for use with a semiconductor process chamber. A series of three-way valves control process fluid flow between process fluid conduits which lead to the process chamber and a divert conduit.Type: ApplicationFiled: March 29, 2019Publication date: October 10, 2019Inventors: Akshay GUNAJI, Tuan Anh NGUYEN, Mayur G. KULKARNI, Sanjeev BALUJA, Kurt LANGELAND
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Publication number: 20190229128Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.Type: ApplicationFiled: February 4, 2019Publication date: July 25, 2019Inventors: Michael Wenyoung TSIANG, Praket P. JHA, Xinhai HAN, Bok Hoen KIM, Sang Hyuk KIM, Myung Hun JU, Hyung Jin PARK, Ryeun Kwan KIM, Jin Chul SON, Saiprasanna GNANAVELU, Mayur G. KULKARNI, Sanjeev BALUJA, Majid K. SHAHREZA, Jason K. FOSTER
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Patent number: 10312076Abstract: Apparatus and methods for depositing a film in a PECVD chamber while simultaneously flowing a purge gas from beneath a substrate support are provided herein. In embodiments disclosed herein, a combined gas exhaust volume circumferentially disposed about the substrate support, below a first volume and above a second volume, draws processing gases from the first volume down over an edge of a first surface of the substrate support and simultaneously draws purge gases from the second volume upward over an edge of a second surface of the substrate support. The gases are than evacuated from the combined exhaust volume through an exhaust port fluidly coupled to a vacuum source.Type: GrantFiled: March 9, 2018Date of Patent: June 4, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Kalyanjit Ghosh, Sanjeev Baluja, Mayur G. Kulkarni
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Publication number: 20190122872Abstract: Systems and methods for depositing a film in a PECVD chamber while reducing residue buildup in the chamber. In some embodiments disclosed herein, a processing chamber includes a chamber body, a substrate support, a showerhead, and one or more heaters configured to heat the showerhead. In some embodiments, the processing chamber includes a controller.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Kalyanjit GHOSH, Sanjeev BALUJA, Mayur G. KULKARNI, Shailendra SRIVASTAVA, Tejas ULAVI, Yusheng ALVIN ZHOU, Amit Kumar BANSAL, Priyanka DASH, Zhijun JIANG, Ganesh BALASUBRAMANIAN, Qiang MA, Kaushik ALAYAVALLI, Yuxing ZHANG, Daniel HWUNG, Shawyon JAFARI
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Patent number: 10242890Abstract: Embodiments of substrate supports with a heater are provided herein. In some embodiments, a substrate support may include a first member to distribute heat to a substrate when present above a first surface of the first member; a heater coupled to the first member and having one or more heating zones to provide heat to the first member; a second member disposed beneath the first member; a tubular body disposed between the first and second members, wherein the tubular body forms a gap between the first and second members; and a plurality of substrate support pins disposed a first distance above the first surface of the first member, the plurality of substrate support pins to support a backside surface of a substrate when present on the substrate support.Type: GrantFiled: August 8, 2011Date of Patent: March 26, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Leon Volfovski, Mayur G. Kulkarni
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Patent number: 10199388Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.Type: GrantFiled: July 19, 2016Date of Patent: February 5, 2019Assignee: APPLIED MATEERIALS, INC.Inventors: Michael Wenyoung Tsiang, Praket P. Jha, Xinhai Han, Bok Hoen Kim, Sang Hyuk Kim, Myung Hun Ju, Hyung Jin Park, Ryeun Kwan Kim, Jin Chul Son, Saiprasanna Gnanavelu, Mayur G. Kulkarni, Sanjeev Baluja, Majid K. Shahreza, Jason K. Foster
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Patent number: 10113231Abstract: A process chamber is provided including a sidewall, a substrate support having an outer ledge, and a gas inlet beneath the substrate support. The process chamber further includes a first liner disposed around a bottom surface of the outer ledge of the substrate support. The first liner has an inner surface separated from the outer ledge of the substrate support by a first gap. The process chamber further includes a flow isolator ring having an inner bottom surface disposed on the outer ledge of the substrate support and an outer bottom surface extending outwardly relative to the inner bottom surface, the outer bottom surface overlying the first gap.Type: GrantFiled: April 25, 2016Date of Patent: October 30, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Dale R. Dubois, Kalyanjit Ghosh, Kien N. Chuc, Mayur G. Kulkarni, Sanjeev Baluja, Yanjie Wang, Sungjin Kim
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Publication number: 20180274095Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.Type: ApplicationFiled: May 30, 2018Publication date: September 27, 2018Inventors: Kalyanjit GHOSH, Mayur G. KULKARNI, Sanjeev BALUJA, Kien N. CHUC, Sungjin KIM, Yanjie WANG
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Publication number: 20180261453Abstract: Apparatus and methods for depositing a film in a PECVD chamber while simultaneously flowing a purge gas from beneath a substrate support are provided herein. In embodiments disclosed herein, a combined gas exhaust volume circumferentially disposed about the substrate support, below a first volume and above a second volume, draws processing gases from the first volume down over an edge of a first surface of the substrate support and simultaneously draws purge gases from the second volume upward over an edge of a second surface of the substrate support. The gases are than evacuated from the combined exhaust volume through an exhaust port fluidly coupled to a vacuum source.Type: ApplicationFiled: March 9, 2018Publication date: September 13, 2018Inventors: Kalyanjit GHOSH, Sanjeev BALUJA, Mayur G. KULKARNI
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Patent number: 10017855Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.Type: GrantFiled: December 18, 2015Date of Patent: July 10, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Kalyanjit Ghosh, Mayur G. Kulkarni, Sanjeev Baluja, Kien N. Chuc, Sungjin Kim, Yanjie Wang
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Publication number: 20180023193Abstract: Embodiments disclosed herein generally relate to systems and methods to prevent free radical damage to sensitive components in a process chamber and optimizing flow profiles. The processing chamber utilizes a cover substrate on lift pins and an inert bottom purge flow to shield the substrate support from halogen reactants. During a clean process, the cover substrate and the purge flow restricts halogen reactants from contacting the substrate support. The method of cleaning includes placing a cover substrate on a plurality of lift pins that extend through a substrate support in a processing chamber, raising the cover substrate via the lift pins to expose a space between the cover substrate and the substrate support, supplying a halogen containing gas into the processing chamber, supplying a second gas through an opening in the processing chamber, and flowing the second gas through the space between the cover substrate and the substrate support.Type: ApplicationFiled: July 19, 2017Publication date: January 25, 2018Inventors: Sanjeev BALUJA, Kalyanjit GHOSH, Ren-Guan DUAN, Mayur G. KULKARNI, Gregory SIU, Praket P. JHA, Deenesh PADHI, Lei GUO, Wei Min CHAN, Ajit BALAKRISHNA