Patents by Inventor Mayur Joshi
Mayur Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9602086Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.Type: GrantFiled: March 25, 2015Date of Patent: March 21, 2017Assignee: Oracle International CorporationInventors: He Huang, Mayur Joshi, Ha Pham, Jin-Uk Shin
-
Publication number: 20160285440Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.Type: ApplicationFiled: March 25, 2015Publication date: September 29, 2016Inventors: He Huang, Mayur Joshi, Ha Pham, Jin-Uk Shin
-
Patent number: 8762087Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.Type: GrantFiled: August 16, 2007Date of Patent: June 24, 2014Assignee: Texas Instruments IncorporatedInventors: Mayur Joshi, Anthony M. Hill, Jose L. Flores
-
Patent number: 8713298Abstract: A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: GrantFiled: January 30, 2012Date of Patent: April 29, 2014Assignee: Round Rock Research, LLCInventor: Mayur Joshi
-
Publication number: 20120131251Abstract: A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: Round Rock Research, LLCInventor: Mayur Joshi
-
Patent number: 8108664Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: GrantFiled: February 9, 2009Date of Patent: January 31, 2012Assignee: Round Rock Research, LLCInventor: Mayur Joshi
-
Publication number: 20090177825Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: ApplicationFiled: February 9, 2009Publication date: July 9, 2009Inventor: Mayur Joshi
-
Patent number: 7516271Abstract: Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry combines the match signals for memory locations to obtain combined match signals; the combination depends on an indicated search width, which can be one of a set of multiples of the memory location width. A priority encoder provides a priority signal indicating a combined match signal that has priority and is asserted; the priority encoder can therefore be smaller than would be necessary to prioritize all the match signals. An address encoder obtains most significant bits of an address code in response to the priority signal. Select circuitry responds to the priority signal by selecting match signals and suppress signals for the combined match signal with priority.Type: GrantFiled: November 6, 2006Date of Patent: April 7, 2009Assignee: Micron Technology, Inc.Inventor: Mayur Joshi
-
Patent number: 7506146Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: GrantFiled: June 8, 2006Date of Patent: March 17, 2009Assignee: Micron Technology, Inc.Inventor: Mayur Joshi
-
Patent number: 7406608Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: GrantFiled: February 5, 2004Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventor: Mayur Joshi
-
Publication number: 20080120065Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.Type: ApplicationFiled: August 16, 2007Publication date: May 22, 2008Inventors: Mayur Joshi, Anthony M. Hill, Jose L. Flores
-
Publication number: 20070113003Abstract: Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry combines the match signals for memory locations to obtain combined match signals; the combination depends on an indicated search width, which can be one of a set of multiples of the memory location width. A priority encoder provides a priority signal indicating a combined match signal that has priority and is asserted; the priority encoder can therefore be smaller than would be necessary to prioritize all the match signals. An address encoder obtains most significant bits of an address code in response to the priority signal. Select circuitry responds to the priority signal by selecting match signals and suppress signals for the combined match signal with priority.Type: ApplicationFiled: November 6, 2006Publication date: May 17, 2007Inventor: Mayur Joshi
-
Patent number: 7152141Abstract: Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry combines the match signals for memory locations to obtain combined match signals; the combination depends on an indicated search width, which can be one of a set of multiples of the memory location width. A priority encoder provides a priority signal indicating a combined match signal that has priority and is asserted; the priority encoder can therefore be smaller than would be necessary to prioritize all the match signals. An address encoder obtains most significant bits of an address code in response to the priority signal. Select circuitry responds to the priority signal by selecting match signals and suppress signals for the combined match signal with priority.Type: GrantFiled: July 31, 2003Date of Patent: December 19, 2006Assignee: Micron Technology, Inc.Inventor: Mayur Joshi
-
Publication number: 20060248326Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: ApplicationFiled: June 8, 2006Publication date: November 2, 2006Inventor: Mayur Joshi
-
Publication number: 20050188282Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.Type: ApplicationFiled: February 5, 2004Publication date: August 25, 2005Inventor: Mayur Joshi
-
Patent number: 6864810Abstract: Non-ordinal conversion is performed between signals with at most one bit asserted and respective codes, such as between priority signals from a content addressable memory (CAM) priority encoder to respective non-ordinal codes. Address encoding includes non-ordinal conversion followed by recoding to obtain ordinal address codes. Signal converting circuitry includes neighboring switching elements such as transistors that are differently offset from neighboring input lines, allowing tight pitch between input lines. To allow for offset, each transistor can have no more than one neighboring transistor. For example, neighboring input lines can have complementary sets of transistors.Type: GrantFiled: July 24, 2003Date of Patent: March 8, 2005Assignee: Micron Technology, Inc.Inventor: Mayur Joshi
-
Publication number: 20050027931Abstract: Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry combines the match signals for memory locations to obtain combined match signals; the combination depends on an indicated search width, which can be one of a set of multiples of the memory location width. A priority encoder provides a priority signal indicating a combined match signal that has priority and is asserted; the priority encoder can therefore be smaller than would be necessary to prioritize all the match signals. An address encoder obtains most significant bits of an address code in response to the priority signal. Select circuitry responds to the priority signal by selecting match signals and suppress signals for the combined match signal with priority.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Inventor: Mayur Joshi
-
Publication number: 20050017880Abstract: Non-ordinal conversion is performed between signals with at most one bit asserted and respective codes, such as between priority signals from a content addressable memory (CAM) priority encoder to respective non-ordinal codes. Address encoding includes non-ordinal conversion followed by recoding to obtain ordinal address codes. Signal converting circuitry includes neighboring switching elements such as transistors that are differently offset from neighboring input lines, allowing tight pitch between input lines. To allow for offset, each transistor can have no more than one neighboring transistor. For example, neighboring input lines can have complementary sets of transistors.Type: ApplicationFiled: July 24, 2003Publication date: January 27, 2005Inventor: Mayur Joshi
-
Patent number: 6831587Abstract: A priority encoder includes static, tree-like product circuitry that responds to input signals, providing subset signals for subsets of the input signals. The subset signals can be for power-of-two subsets such as 1, 2, 4, 8, etc. input signals. The priority encoder also includes dynamic, tree-like priority circuitry that responds to the subset signals, providing priority signals, each indicating whether a respective input line is asserted and has priority. Each output line of the priority circuitry can be controlled by a group of transistors in series, with a respective transistor for each of a non-redundant set of the subset signals. A priority encoder can include a number of lower level priority encoding circuits and one upper level priority encoding circuit that receives overall signals from the lower circuits.Type: GrantFiled: July 31, 2003Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventor: Mayur Joshi