Patents by Inventor Mazhar Memon
Mazhar Memon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200257553Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: ApplicationFiled: January 8, 2020Publication date: August 13, 2020Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Publication number: 20200201648Abstract: Execution of multiple execution streams is scheduled on a plurality of coprocessors. A software layer located logically between applications and the coprocessors determines dependencies within the execution streams, each said dependency being a condition in one of the execution streams that must be satisfied in order for execution of at least one other of the execution streams to proceed on corresponding ones of the coprocessors. The dependencies are then represented in a data structure and an optimized execution schedule is determined for the execution streams according to the dependencies. Simultaneous execution of a plurality of the execution streams is then dynamically reordered according to the optimized execution schedule.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Aidan CULLY
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Patent number: 10534639Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: GrantFiled: July 6, 2017Date of Patent: January 14, 2020Assignee: Bitfusion.io, Inc.Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Publication number: 20190213062Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: ApplicationFiled: March 16, 2019Publication date: July 11, 2019Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Publication number: 20190114254Abstract: At least one application runs on a hardware platform that includes a plurality of coprocessors, each of which has a respective internal memory space. An intermediate software layer (MVL) is transparent to the application and intercepts calls for coprocessor use. If the data corresponding to an application's call, or separate calls from different entities (including different applications) to the same coprocessor, to the API of a target coprocessor, cannot be stored within the available internal memory space of the target coprocessor, but comprises data subsets that individually can, the MVL intercepts the call response to the application/entities and indicates that the target coprocessor can handle the request. The MVL then transfers the data subsets to the target coprocessor as needed by the corresponding kernel(s) and swaps out each data subset to the internal memory of another coprocessor to make room for subsequently needed data subsets.Type: ApplicationFiled: October 16, 2017Publication date: April 18, 2019Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Zheng LI
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Patent number: 10261847Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: GrantFiled: March 7, 2017Date of Patent: April 16, 2019Assignee: Bitfusion.io, Inc.Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Publication number: 20190012197Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Publication number: 20170293510Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: ApplicationFiled: March 7, 2017Publication date: October 12, 2017Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Patent number: 8751676Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.Type: GrantFiled: October 29, 2012Date of Patent: June 10, 2014Assignee: Intel CorporationInventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
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Patent number: 8645596Abstract: Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.Type: GrantFiled: December 30, 2008Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Amit Kumar, Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Theodore Willke, II
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Publication number: 20130055263Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.Type: ApplicationFiled: October 29, 2012Publication date: February 28, 2013Inventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
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Patent number: 8307105Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.Type: GrantFiled: June 30, 2011Date of Patent: November 6, 2012Assignee: Intel CorporationInventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
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Patent number: 8209559Abstract: Techniques are described to provide the capability to halt execution of a thread by a processor and potentially lower power consumption of the processor while responding to events in a timely manner. An operating system provided system call allows for identification of events that cause the execution of the thread to resume. A processor core uses a signal mask and translation unit that monitors for the identified events. In the event an event is detected, the thread unhalts and determines a manner to process the event.Type: GrantFiled: December 24, 2008Date of Patent: June 26, 2012Assignee: Intel CorporationInventors: Mazhar Memon, Steven King
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Publication number: 20110258283Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Inventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
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Patent number: 7996548Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.Type: GrantFiled: December 30, 2008Date of Patent: August 9, 2011Assignee: Intel CorporationInventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
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Publication number: 20100169501Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Inventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
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Publication number: 20100169528Abstract: Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Inventors: Amit Kumar, Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Theodore Willke, II
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Publication number: 20100162014Abstract: Techniques are described to provide the capability to halt execution of a thread by a processor and potentially lower power consumption of the processor while responding to events in a timely manner. An operating system provided system call allows for identification of events that cause the execution of the thread to resume. A processor core uses a signal mask and translation unit that monitors for the identified events. In the event an event is detected, the thread unhalts and determines a manner to process the event.Type: ApplicationFiled: December 24, 2008Publication date: June 24, 2010Inventors: Mazhar Memon, Steven King