Abstract: An integrated circuit layout is provided, which includes a base platform for an integrated circuit, a processor hardmac and a support memory. The base platform includes a memory matrix having leaf cells arranged in rows and columns. Each column of leaf cells has interface pins that are routed to a common matrix edge and have a common pin order along the matrix edge. The processor hardmac is placed along the memory matrix and has a hardmac edge adjacent the memory matrix edge and a plurality of interface pins for interfacing with corresponding interface pins of the memory matrix. The interface pins of the processor hardmac have the same pin order along the hardmac edge as the interface pins along the matrix edge. The support memory for the processor hardmac is mapped to a portion of the memory matrix along the hardmac edge.