Abstract: A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

Abstract: A trench-gate semiconductor device and a manufacturing method therefore is provided. The device includes one or more unit cells, each unit cell includes a trench a first oxide layer arranged on an upper portion of a side wall of the trench, the first oxide layer forming a gate oxide of the unit cell, and a second oxide layer arranged on a lower portion of the side wall and on a bottom of the trench.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate structure, a gate structure, a drift region, a drain region in the substrate structure, two isolation structures at opposite sides of the drift region, wherein the drift region has a first width, the isolation structure has a second width, a ratio of the first width to the second width is in a range from 1 to 4. The semiconductor device further includes a super-junction doped structure in the drift region and including a plurality of first-conductive-type doped sub-regions and a plurality of second-conductive-type doped sub-regions which are alternately disposed. Widths of the plurality of first-conductive-type doped sub-regions decrease from the gate structure to the drain region, and widths of the plurality of second-conductive-type doped sub-regions also decrease from the gate structure to the drain region.

Abstract: A level shifter is provided. The level shifter is located between a high-side circuit area and a low-side circuit area and includes a substrate, a buried island, and an isolation structure. The buried island has a first conductivity type and is located in the substrate. The isolation structure has a second conductivity type, is located in the substrate and surrounds the buried island. In addition, a dimension of the isolation structure near the high-side circuit area is different from a dimension of the isolation structure near the low-side circuit area. A semiconductor device including the level shifter is also provided.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate structure including a high side region, a low side region, a level shift region and an isolation region. The low side region is separated from the high side region. The level shift region and the isolation region are disposed between the low side region and the high side region. The level shift region is separated from the high side region by the isolation region. A doped isolation region, which is disposed in the isolation region, includes a first doped portion and a second doped portion adjacent to the first doped portion. The depth of the first doped portion is decreased linearly along a first direction from the isolation region to the level shift region. The depth of the second doped portion is decreased linearly along a second direction from the isolation region to the high side region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate structure, a gate structure, a drift region, a drain region in the substrate structure, two isolation structures at opposite sides of the drift region, wherein the drift region has a first width, the isolation structure has a second width, a ratio of the first width to the second width is in a range from 1 to 4. The semiconductor device further includes a super-junction doped structure in the drift region and including a plurality of first-conductive-type doped sub-regions and a plurality of second-conductive-type doped sub-regions which are alternately disposed. Widths of the plurality of first-conductive-type doped sub-regions decrease from the gate structure to the drain region, and widths of the plurality of second-conductive-type doped sub-regions also decrease from the gate structure to the drain region.

Abstract: A level shifter is provided. The level shifter is located between a high-side circuit area and a low-side circuit area and includes a substrate, a buried island, and an isolation structure. The buried island has a first conductivity type and is located in the substrate. The isolation structure has a second conductivity type, is located in the substrate and surrounds the buried island. In addition, a dimension of the isolation structure near the high-side circuit area is different from a dimension of the isolation structure near the low-side circuit area. A semiconductor device including the level shifter is also provided.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: A high-voltage semiconductor device is disclosed. The high-voltage semiconductor device includes a gate structure on a substrate structure. A drain doped region and a source doped region are located close to opposite sides of the gate structure. The source doped region, the gate structure and the drain doped region are located close to a top surface of the substrate structure. A super junction doped structure is located close to the drain doped region. The super junction doped structure includes a plurality of first conductive type doped sub-regions extending along a first direction and arranged along a second direction. A plurality of second conductive type doped sub-regions extends along the first direction and is arranged staggered with the first conductive type doped sub-regions. The widths of the first conductive type doped sub-regions and the second conductive type doped sub-regions along the second direction decrease linearly along the second direction.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate structure including a high side region, a low side region, a level shift region and an isolation region. The low side region is separated from the high side region. The level shift region and the isolation region are disposed between the low side region and the high side region. The level shift region is separated from the high side region by the isolation region. A doped isolation region, which is disposed in the isolation region, includes a first doped portion and a second doped portion adjacent to the first doped portion. The depth of the first doped portion is decreased linearly along a first direction from the isolation region to the level shift region. The depth of the second doped portion is decreased linearly along a second direction from the isolation region to the high side region.

Abstract: A semiconductor device includes a metal-oxide-semiconductor field effect transistor (MOSFET), in which parasitic silicon controlled rectifier (SCR) equivalent circuits are formed in the MOSFET, and the MOSFET further includes a drain region. The drain region includes P-type heavily doped regions which are different from each other, in which the P-type heavily doped regions are respectively operated as anodes of the SCR equivalent circuits.

Abstract: A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer.

Abstract: The semiconductor device includes a first semiconductor layer of a first conductivity type, an insulated gate structure, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, and a lightly doped semiconductor region of the second conductivity type. The insulated gate structure is formed in a trench configuration recessed into the first semiconductor layer. The first semiconductor region, the second semiconductor region, and the lightly doped semiconductor region are formed in the first semiconductor layer. The second semiconductor region contacts the first semiconductor region and the insulated gate structure. The second semiconductor region is formed on the lightly doped semiconductor region. The lightly doped semiconductor region is formed between and contacts the first semiconductor region and the insulated gate structure. A method of manufacturing a semiconductor device is also disclosed herein.

Abstract: A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region.

Abstract: A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region.

Abstract: A semiconductor device includes a metal-oxide-semiconductor field effect transistor (MOSFET), in which parasitic silicon controlled rectifier (SCR) equivalent circuits are formed in the MOSFET, and the MOSFET further includes a drain region. The drain region includes P-type heavily doped regions which are different from each other, in which the P-type heavily doped regions are respectively operated as anodes of the SCR equivalent circuits.

Abstract: A metal oxide semiconductor field transistor including a gate electrode, a gate dielectric layer, a source region, a drain region, and a top doped region are provided. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounded the drain region. The gate electrode is located above the substrate between the source region and the drain region. The gate dielectric layer is located between the gate electrode and the substrate. The top doped region of a second conductivity type is located in the substrate between the gate electrode and the drain region. The top doped region includes at least three regions. Each of the three regions has a dopant concentration gradient and a concentration gradually decreased from a region adjacent the gate electrode to a region adjacent the drain region.