Abstract: A method of automatically detecting delay due to cable length between network nodes coupled to a two-wire communication bus of a network. The method includes establishing, by a first node of the network, a first specified delay value of a variable delay setting; discovering a next node on the communication bus using a variable delay setting including the delay setting established at the first specified delay value; after discovering the next node, changing the variable delay setting until the next node drops off the communication bus at a second specified delay value of the variable delay setting; and setting a communication delay setting between the first node and the next node using the first and second specified delay values.

Abstract: Systems and techniques for line diagnostics. In particular, disclosed herein are systems and techniques for line diagnostics that sense a state of an electrical cable by using multiple, time-spaced stimuli and detecting their signal reflection time at different threshold levels. Information derived from multiple reflections may be used to determine cable characteristics (e.g., “wire short,” “wire open,” “correctly terminated,” etc.). The systems and techniques disclosed herein may advantageously require less complex hardware and implementation algorithms than conventional time domain reflectometry (TDR) approaches, and thus may be implemented in settings in which TDR was previously unsuitable. Further, if a cable issue is detected, the systems and techniques disclosed herein may determine the approximate location of the cable issue along the cable, accelerating correction of the issue.

Abstract: Computer-implemented methods, systems and computer-readable media for building and using an artificial intelligence model for secure biometric authentication. Utilizing difference vectors, the model securely relates output vectors generated from noisy biometric data of a plurality of enrolled users to pre-defined fixed points in a vector space.

Abstract: A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.

Abstract: Embodiments of the present disclosure perform procedures that manipulate a memory system's local cache line eviction policy so that critical “dirty” cache lines are evicted from last level caches as late as possible. Embodiments can selectively handle cache lines in a manner that can renew the liveliness of “dirty” cache lines so that a local “least recently used” (LRU) eviction policy treats them as though they were recently accessed rather than evicting them. Embodiments perform read operations and manipulate the age or “active” status of cache lines by performing procedures which modify “dirty” cache lines to make them appear active to the processor. Embodiments of the present disclosure can also invalidate “clean” cache lines so that “dirty” lines automatically stay in the cache.

Abstract: A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.

Abstract: A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.

Abstract: A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is stored. The processor may be configured to determine whether to swap physical locations of data stored at logical block addresses in the first logical block address collection and physical locations of data stored at logical block addresses in the second logical block address collection. The processor may be further configured to, in response to determining to swap the physical locations of the data, swap the physical locations of the data stored at the logical block addresses in the first logical block address collection and the physical locations of the data stored at the logical block addresses in the second logical block address collection.

Abstract: A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is stored. The processor may be configured to determine whether to swap physical locations of data stored at logical block addresses in the first logical block address collection and physical locations of data stored at logical block addresses in the second logical block address collection. The processor may be further configured to, in response to determining to swap the physical locations of the data, swap the physical locations of the data stored at the logical block addresses in the first logical block address collection and the physical locations of the data stored at the logical block addresses in the second logical block address collection.

Abstract: Embodiments of the present disclosure perform procedures that manipulate a memory system's local cache line eviction policy so that critical “dirty” cache lines are evicted from last level caches as late as possible. Embodiments can selectively handle cache lines in a manner that can renew the liveliness of “dirty” cache lines so that a local “least recently used” (LRU) eviction policy treats them as though they were recently accessed rather than evicting them. Embodiments perform read operations and manipulate the age or “active” status of cache lines by performing procedures which modify “dirty” cache lines to make them appear active to the processor. Embodiments of the present disclosure can also invalidate “clean” cache lines so that “dirty” lines automatically stay in the cache.

Abstract: A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.