Abstract: The present invention relates to a new device for selective arsenic sensing using electrochemically reduced graphene oxide (ERGO) based reusable flexible electrode strip. Active electrode of the device was prepared by a very simple method in which the thin film of graphene oxide (GO) was reduced electrochemically at a low DC potential (0 to -1.5 V). The said device selectively detects As3+ in field water sample within a wide range of concentrations with a limit of detection of less than 25 ppb. More importantly, the selectivity of the electrode is independent of conductivity and TDS levels of measured field water samples which were collected from various parts of India. Selective detection of As3+ by ERGO was controlled by optimizing the surface electronic conductivity through structural modification of it during electroreduction process.

Abstract: Reduced graphene oxide@polystyrene (RGO—PS) composite was synthesized using reduced graphene oxide (RGO), styrene monomer and divinylbenzene through an in-situ polymerization process. The RGO—PS composite was functionalized with sulfonate and quaternary amine functionalities for making positive and negative integrated electro-adsorbent-ion exchange resins (EAIERs), respectively. These EAIERs ‘molecular constructs’ were used as CDI electrodes and desalination was performed for the removal of different ions. A high electro-adsorption capacity of ˜15.93 mg/g for Cl? using 802 ?S NaCl solution was observed in laboratory batch experiments which was much higher than the adsorption capacity of RGO electrodes reported earlier (˜2-3 mg/g).

Abstract: In making inlaid structures in a semiconductor device, such as vias and trenches, a cavity is formed to expose an underlying metal layer. A degas step is then performed on the device which heats the device. If the device is then subjected to an RF sputter clean, some of the exposed metal is splattered onto the sidewall of the cavity. The problem that was discovered is that if the sidewall is too hot, this metal agglomerates. These agglomerations on the sidewall operate to block the continuous deposition of a seed layer. If the seed layer is not continuous, some portions of the seed layer may not receive the voltage necessary for the subsequent deposition by electroplating, leaving voids. To avoid these agglomerations, the device is actively cooled after the degas and before the sputtering commences so that agglomerations are not formed on the sidewall during the sputter clean.

Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.