Patents by Inventor Md. Tofizur Rahman

Md. Tofizur Rahman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437567
    Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Justin Brockman, Christopher Wiegand, MD Tofizur Rahman, Daniel Ouelette, Angeline Smith, Juan Alzate Vinasco, Charles Kuo, Mark Doczy, Kaan Oguz, Kevin O'Brien, Brian Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11404630
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Md Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Justin S. Brockman, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11374164
    Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Kaan Oguz, Christopher Wiegand, Angeline Smith, Noriyuki Sato, Kevin O'Brien, Benjamin Buford, Ian Young, Md Tofizur Rahman
  • Patent number: 11031545
    Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz
  • Patent number: 10868233
    Abstract: Strain engineering of perpendicular magnetic tunnel junctions (PMTJs) is described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz, Oleg Golonzka, Justin S. Brockman, Kevin P. O'Brien, Brian S. Doyle, Kaan Oguz, Tahir Ghani, Mark L. Doczy
  • Patent number: 10847714
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, Md Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10804460
    Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Daniel B. Bergstrom, Justin S. Brockman, Oleg Golonzka, Tahir Ghani
  • Patent number: 10770651
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 10732217
    Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Kaan Oguz, Christopher J. Wiegand, Mark L. Doczy, Brian S. Doyle, MD Tofizur Rahman, Oleg Golonzka, Tahir Ghani
  • Patent number: 10636960
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz
  • Publication number: 20200105324
    Abstract: A magnetic tunnel junction (MTJ) for use in a magnetic spin orbit torque random access memory device (SOT MRAM) is described. Magnetic tunnel junctions described herein include a multi-magnet free layer over a spin orbit torque electrode. The multi-magnet free layer includes at least three sub-layers: a first magnetic sub-layer in direct contact with the SOT electrode having a first magnetic stability, a second magnetic sub-layer having a second magnetic stability greater than the first magnetic stability, and a magnetic coupling layer between the first and second sub-layers.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Angeline Smith, Sasikanth Manipatruni, MD Tofizur Rahman, Noriyuki Sato, Tanay Gasovi, Christopher Wiegand, Ian Young
  • Patent number: 10559744
    Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Brian Maertz, Christopher J. Wiegand, Daniel G. Oeullette, Md Tofizur Rahman, Oleg Golonzka, Justin S. Brockman, Tahir Ghani, Brian S. Doyle, Kevin P. O'Brien, Mark L. Doczy, Kaan Oguz
  • Publication number: 20200006637
    Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Tanay GOSAVI, Sasikanth MANIPATRUNI, Chia-Ching LIN, Kaan OGUZ, Christopher WIEGAND, Angeline SMITH, Noriyuki SATO, Kevin O'BRIEN, Benjamin BUFORD, Ian YOUNG, MD Tofizur RAHMAN
  • Publication number: 20190378972
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 12, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190334079
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Application
    Filed: December 30, 2016
    Publication date: October 31, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Justin S. BROCKMAN, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190288190
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10418415
    Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Wiegand, Oleg Golonzka, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Kevin P. O'Brien, Kaan Oguz, Tahir Ghani, Satyarth Suri
  • Publication number: 20190280188
    Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: September 12, 2019
    Inventors: Justin BROCKMAN, Christopher WIEGAND, MD Tofizur RAHMAN, Daniel OUELETTE, Angeline SMITH, Juan ALZATE VINASCO, Charles KUO, Mark DOCZY, Kaan OGUZ, Kevin O'BRIEN, Brian DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190221734
    Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, MD Tofizur Rahman, Brian Maertz
  • Patent number: 10340445
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman