Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Systems and methods for a network device to update timing packets to reflect delay are provided. A timing packet processor is externally connected to the network device. All timing packets are processed by the timing packet processor. The timing packets are updated to reflect an estimate of delay introduced by the network device.

Abstract: A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Port multiplexing apparatus and methods are disclosed. Time slots in a time division multiplexing (TDM) scheme are allocated to transfer signals such as Ethernet or Fiber Channel packets associated with ports of a signal processing device. Signals associated with multiple ports are transferred between those ports and another signal processing device over a single logical link in accordance with the time slot allocation. An indication of the time slot allocation may also be transferred on the link, illustratively by replacing protocol overhead traffic to be transmitted on the link with allocation information. At a receiver, the replaced protocol overhead traffic may be substituted back into a received multiplexed signal. A port multiplexing apparatus may be controllable to operate in a multiplexing mode or in a non-multiplexing mode. Aspects of the invention may also be embodied in other forms, such as in a data structure stored on a machine-readable medium.

Abstract: A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.

Abstract: Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

Abstract: Systems and methods for a network device to update timing packets to reflect delay are provided. A timing packet processor is externally connected to the network device. All timing packets are processed by the timing packet processor. The timing packets are updated to reflect an estimate of delay introduced by the network device.

Abstract: The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble.

Abstract: The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble.