Abstract: An inductor structure includes a first quadrupole inductor, and a second quadrupole inductor, wherein the second quadrupole inductor overlaps the first quadrupole inductor. In certain aspects, the inductor structure may be included in a filter, which may also include one or more capacitors coupled to the inductor structure.

Abstract: An inductor structure includes a first quadrupole inductor, and a second quadrupole inductor, wherein the second quadrupole inductor overlaps the first quadrupole inductor. In certain aspects, the inductor structure may be included in a filter, which may also include one or more capacitors coupled to the inductor structure.

Abstract: An inductor structure has a first terminal and a second terminal, and includes a conductor path between the first terminal and the second terminal. The conductor path includes a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, and a sixth inductor. The conductor path may be configured such that, when a current flows from the first terminal to the second terminal, the current flows in a first direction in the first inductor, the third inductor, and the fifth inductor, and the current flows in a second direction in the second inductor, the fourth inductor, and the sixth inductor. The first direction may be clockwise and the second direction may be counterclockwise, or vice versa.

Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.

Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.

Abstract: Methods and apparatuses, wherein the method includes creating a surface mount socket pin for integrated circuit packaging. The method couples a first conductive element to a second conductive element, wherein the closed loop conductor is configured to provide two paths between the first conductive element and second conductive element, wherein a central region of the closed loop conductor is configured to engage with a plurality of symmetrical bumps in a mold to secure the closed loop conductor, wherein the closed loop conductor is elastic.

Abstract: A transmitter front-end for wireless chip-to-chip communication, and potentially for other, longer range (e.g., several meters or several tens of meters) device-to-device communication, is disclosed. The transmitter front-end includes a distributed power amplifier capable of providing an output signal with sufficient power for wireless transmission by an on-chip or on-package antenna to another nearby IC chip or device located several meters or several tens of meters away. The distributed power amplifier can be fully integrated (i.e., without using external components, such as bond wire inductors) on a monolithic silicon substrate using, for example, a complementary metal oxide semiconductor (CMOS) process.

Abstract: A transmitter front-end for wireless chip-to-chip communication, and potentially for other, longer range (e.g., several meters or several tens of meters) device-to-device communication, is disclosed. The transmitter front-end includes a distributed power amplifier capable of providing an output signal with sufficient power for wireless transmission by an on-chip or on-package antenna to another nearby IC chip or device located several meters or several tens of meters away. The distributed power amplifier can be fully integrated (i.e., without using external components, such as bond wire inductors) on a monolithic silicon substrate using, for example, a complementary metal oxide semiconductor (CMOS) process.