Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality of indicators for the memory block. The indicator is saved and later retrieved during a read operation.

Abstract: Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation.

Abstract: Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed.

Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell.

Abstract: A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell.

Abstract: An apparatus having a code strip carrier that is illuminated by an illumination system and a plurality of read heads is disclosed. Each code track includes a plurality of dark and light stripes. Each read head is positioned to detect light from a corresponding one of the code tracks as that code track moves relative to the read head, the read head generating a signal indicative of the intensity of light reaching that read head. One of the code tracks includes a first absolute position track that provides an indication of the absolute position value when the code strip carrier is at each of a plurality of predetermined absolute positions relative to the origin position. A different one of the code tracks includes an incremental position track for generating a digital value indicative of a displacement of the code strip carrier relative to the last predetermined absolute position.