Abstract: The present invention provides a method for fabricating a MOS transistor (100) with suppression of edge transistor effect. In one embodiment of an NMOS, an elongate implant limb (110, HOa, 114) extends from each of two sidewalls (14a, 14b) of a p-type well (14) to partially wrap around each respective longitudinal end of the gate (20) and to overlay a portion thereof. In another embodiment, the elongate implant limb (110, 110a) extends into the drain/source drift region (32, 42). The NMOS transistor (100) thus fabricated allows the NMOS transistor to operate at relatively high voltages with reduced drain leakage current but with no additional masks or process time in the process integration.