Patents by Inventor Meenatchi Jagasivamani
Meenatchi Jagasivamani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8934291Abstract: A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.Type: GrantFiled: September 17, 2007Date of Patent: January 13, 2015Assignee: Intel CorporationInventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Enzo M. Donze
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Patent number: 8570795Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: GrantFiled: June 28, 2012Date of Patent: October 29, 2013Assignee: Intel CorporationInventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Publication number: 20120268984Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Patent number: 8228723Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: GrantFiled: August 8, 2011Date of Patent: July 24, 2012Assignee: Intel CorporationInventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Publication number: 20110292721Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Patent number: 8064265Abstract: Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.Type: GrantFiled: January 31, 2008Date of Patent: November 22, 2011Assignee: Intel CorporationInventors: Meenatchi Jagasivamani, Richard Fackenthal, Ferdinando Bedeschi, Enzo Donze
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Patent number: 8018763Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: GrantFiled: December 9, 2010Date of Patent: September 13, 2011Assignee: Intel CorporationInventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Patent number: 7940553Abstract: A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.Type: GrantFiled: December 30, 2008Date of Patent: May 10, 2011Assignee: STMicroelectronics S.r.l.Inventors: Patrick Wu, Richard Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Enzo Michele Donze
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Publication number: 20110080777Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: ApplicationFiled: December 9, 2010Publication date: April 7, 2011Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Patent number: 7885099Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: GrantFiled: September 18, 2007Date of Patent: February 8, 2011Assignee: Intel CorporationInventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
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Patent number: 7869269Abstract: A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.Type: GrantFiled: September 12, 2008Date of Patent: January 11, 2011Assignee: STMicroelectronics S.r.l.Inventors: Enzo Michele Donzè, Ferdinando Bedeschi, Meenatchi Jagasivamani
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Patent number: 7848133Abstract: A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory.Type: GrantFiled: December 31, 2007Date of Patent: December 7, 2010Assignee: Intel CorporationInventors: Richard Fackenthal, Meenatchi Jagasivamani
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Publication number: 20100169740Abstract: In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: STMicroelectronics S.r.I.Inventors: Meenatchi Jagasivamani, Anthony Ko, Rich E. Fackenthal, Ferdinando Bedeschi, Enzo Donze, Ravi Gutala
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Publication number: 20100165714Abstract: A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: STMICROELECTRONICS S.R.L.Inventors: Patrick Wu, Richard Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Enzo Michele Donze
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Publication number: 20090196092Abstract: Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Meenatchi Jagasivamani, Richard Fackenthal, Ferdinando Bedeschi, Enzo Donze
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Publication number: 20090168503Abstract: A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Richard Fackenthal, Meenatchi Jagasivamani
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Publication number: 20090109738Abstract: A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.Type: ApplicationFiled: September 12, 2008Publication date: April 30, 2009Applicant: STMICROELECTRONICS S.R.L.Inventors: Enzo Michele Donze, Ferdinando Bedeschi, Meenatchi Jagasivamani
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Publication number: 20090073751Abstract: A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.Type: ApplicationFiled: September 17, 2007Publication date: March 19, 2009Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Enzo M. Donze
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Publication number: 20090073752Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.Type: ApplicationFiled: September 18, 2007Publication date: March 19, 2009Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze