Patents by Inventor Meera S. Mohan

Meera S. Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIELD EFFECT TRANSISTORS WITH REDUCED PARASITIC RESISTANCES AND METHOD
    Publication number: 20180247936
    Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: SHISHIR K. RAY, BHARAT V. KRISHNAN, JINPING LIU, MEERA S. MOHAN, JOSEPH K. KASSIM
  • Field effect transistors with reduced parasitic resistances and method
    Patent number: 10062692
    Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir K. Ray, Bharat V. Krishnan, Jinping Liu, Meera S. Mohan, Joseph K. Kassim