Abstract: Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Abstract: Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Abstract: Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information.

Abstract: Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information.

Abstract: A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.