Patents by Inventor Meghraj Kalase

Meghraj Kalase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated timing closure on circuit designs
    Patent number: 11714950
    Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 1, 2023
    Assignee: XILINX, INC.
    Inventors: Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Srinivasan Dasasathyan, Padmini Gopalakrishnan, Frederic Revenu, Veena Johar, Pawan Kumar Singh, Mohit Sharma, Kameshwar Chandrasekar
  • AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS
    Publication number: 20230034736
    Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.
    Type: Application
    Filed: July 22, 2021
    Publication date: February 2, 2023
    Applicant: Xilinx, Inc.
    Inventors: Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Srinivasan Dasasathyan, Padmini Gopalakrishnan, Frederic Revenu, Veena Johar, Pawan Kumar Singh, Mohit Sharma, Kameshwar Chandrasekar
  • System and method for an electronic design tool providing automated guidance and interface for circuit design processing
    Patent number: 10867093
    Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Xilinx, Inc.
    Inventors: John Blaine, Srinivasan Dasasathyan, Meghraj Kalase, Frederic Revenu, Veeresh Pratap Singh, Satish Bachina, Shail Bains, Padmini Gopalakrishnan, Sumit Nagpal, Gaurav Dutt Sharma