Abstract: One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch instruction is stored as the history information, In the case that there are a plurality of branch addresses to be stored at a storing place, when a first branch address is stored at a storing place, a second branch address is stored at a storing place in accordance with selection information updated by the updating unit.

Abstract: The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

Abstract: To maintain data consistency in an information processing apparatus in which a nodes are coupled, takeout information indicating that data of the node is taken out to a secondary memory of another node is stored in a directory of each node. When a cache miss occurs during a memory access to a secondary memory of one node, the one node judges whether a destination of the memory access is a main or the secondary memory thereof. If the memory access is destination is the main or secondary memory of the one node, the directory is indexed and retrieved to judge whether a directory hit occurs, and if no directory hit occurs, a memory access is performed by the one node based on the memory access.

Abstract: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

Abstract: A return address in response to a return instruction corresponding to a call instruction is stored in a return address stack when a branch history detects presence of the call instruction. When the branch history detects the presence of the return instruction before a branch reservation station completes executing the call instruction, the return address in response to the return instruction is not stored in the return address stack. If so, an output selection circuit predicts a correct return target using information stored in the return address stack.

Abstract: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative memory device. The invention includes a selector for selecting one entry from all entries of a past branch history memory section if all entries of the past branch history memory section are in use when a branch history about a new branch instruction is registered into the past branch history memory section and a replacing section for registering the branch history about the new branch instruction into one entry selected by said selector, wherein the selector has a first selecting function of selecting one entry based on the branch history held by the past branch history memory section.

Abstract: A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed simultaneously, and a parallel branch predicting unit that performs branch prediction in parallel for the branch instructions completed simultaneously, based on the branch information received and a branch history of the respective branch instructions, to obtain branch prediction results.

Abstract: One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch instruction is stored as the history information, In the case that there are a plurality of branch addresses to be stored at a storing place, when a first branch address is stored at a storing place, a second branch address is stored at a storing place in accordance with selection information updated by the updating unit.

Abstract: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

Abstract: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.

Abstract: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative memory device. The invention includes a selector for selecting one entry from all entries of a past branch history memory section if all entries of the past branch history memory section are in use when a branch history about a new branch instruction is registered into the past branch history memory section and a replacing section for registering the branch history about the new branch instruction into one entry selected by said selector, wherein the selector has a first selecting function of selecting one entry based on the branch history held by the past branch history memory section.

Abstract: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.

Abstract: The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by enabling an unnecessary entry to be selected as an entry, which is an object of replacement, without using new resources in a full-associative memory device. The invention includes a selector for selecting one entry from all entries of a past branch history memory section if all entries of the past branch history memory section are in use when a branch history about a new branch instruction is registered into the past branch history memory section and a replacing section for registering the branch history about the new branch instruction into one entry selected by said selector, wherein the selector has a first selecting function of selecting one entry based on the branch history held by the past branch history memory section.

Abstract: A storage device in a set associative system includes N-pieces (N is an integer of 2 or larger) of ways each having a plurality of entries containing at least replace flags and predetermined data, an acquisition unit acquiring the replace flags contained in the entries specified by the same address from the N-pieces of ways, and a selection unit selecting a replace target way on the basis of the replace flags acquired by the acquisition unit.

Abstract: A return address in response to a return instruction corresponding to a call instruction is stored in a return address stack when a branch history detects presence of the call instruction. When the branch history detects the presence of the return instruction before a branch reservation station completes executing the call instruction, the return address in response to the return instruction is not stored in the return address stack. If so, an output selection circuit predicts a correct return target using information stored in the return address stack.

Abstract: The present invention is a branch prediction device comprising a branch history storage device for storing branch history information in order to predict branch behavior, an error detection mechanism for detecting the reading error of the branch history information, and an erasure mechanism for erasing the storage region of the branch history information in which the reading error is detected.

Abstract: The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

Abstract: A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed simultaneously, and a parallel branch predicting unit that performs branch prediction in parallel for the branch instructions completed simultaneously, based on the branch information received and a branch history of the respective branch instructions, to obtain branch prediction results.

Abstract: A memory access method is employed in a multiprocessor system which includes a plurality of system modules coupled via a crossbar module, where each of the system modules includes a buffer which holds data and a plurality of processors having a cache memory which temporarily holds data. The memory access method includes a step, responsive to a read request from a processor within an arbitrary system module, holding data preread from a system module other than the arbitrary system module in a buffer within the crossbar module.

Abstract: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.