Abstract: An architecture is presented that controls access to secure data via biometric verification. The system comprises a memory module that communicates with biometric data to establish a heightened level of security for controlling access to data stored in the non-volatile memory. The memory module includes a security processor, non-volatile memory, and volatile memory. The security processor provides for concurrent processing of security protocols, provides a secure execution environment within the memory module to evaluate and store biometric data, communicates with the biometric data sensors to fetch the biometric data, and analyzes the biometric data to control access to data stored in the non-volatile memory. Specifically, biometric data is input and communicated to the security processor, then compared against the existing biometric templates stored in the non-volatile memory. If the data matches, verification is sent to the external processor and the user is granted access to the secure assets.

Abstract: An architecture is presented that controls access to secure data via biometric verification. The system comprises a memory module that communicates with biometric data to establish a heightened level of security for controlling access to data stored in the non-volatile memory. The memory module includes a security processor, non-volatile memory, and volatile memory. The security processor provides for concurrent processing of security protocols, provides a secure execution environment within the memory module to evaluate and store biometric data, communicates with the biometric data sensors to fetch the biometric data, and analyzes the biometric data to control access to data stored in the non-volatile memory. Specifically, biometric data is input and communicated to the security processor, then compared against the existing biometric templates stored in the non-volatile memory. If the data matches, verification is sent to the external processor and the user is granted access to the secure assets.

Abstract: A low voltage EPROM which increases its reading speed by charging a word line to a voltage higher than vcc during a read operation. Two voltage pumps, which alternately place charge on a word line, receive control signals of opposite phase from a temperature insensitive oscillator. The voltage from the two voltage pumps passes through a zero threshold voltage n-type pass device to a word line. The zero threshold voltage n-type pass device receives its control signal from a third voltage pump. In order to make the low voltage EPROM compatible with standard 5V programmers, each output driving circuit consists of a large output driver used under low voltage V.sub.cc conditions and a smaller output driver used under standard 5V V.sub.cc conditions.