Abstract: An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mode selection filter, a phase locked loop (PLL) and a drift compensation circuit communicatively coupled between the mode selection filter and the PLL. The mode selection filter provides a mode selection result to the drift compensation circuit. The drift compensation circuit phase modulates the mode selection result in a vector based coordinate system to maintain a drift compensated mode selection result within a locking bandwidth of the PLL, and to minimize phase shifting from accumulating phase drift. The PLL detects a phase difference between the drift compensated mode selection result and a reference signal, for use in maintaining the PLL in a phase lock with the reference signal, in particular over wide operational temperature ranges.

Abstract: System and methods of using an Artificial Intelligence (“AI”) trained model for classifying a patient's gait include receiving a video of a patient on the gait analysis device; classifying the patient's gait using a machine learning process on the gait analysis device; wherein the machine learning process is generated from an Artificial Intelligence (“AI”) trained model comprising: a key point trained model configured to generate a set of key points on a patient's body; an Angle-Based Approach configured to use the set of key points to classify the patient's gait based on angle calculations between key points; and a Key Point Path Track-Based Approach configured to use the key points to classify the patient's gait based on a patient's stance phase and swing phase.

Abstract: An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mode selection filter, a phase locked loop (PLL) and a drift compensation circuit communicatively coupled between the mode selection filter and the PLL. The mode selection filter provides a mode selection result to the drift compensation circuit. The drift compensation circuit phase modulates the mode selection result in a vector based coordinate system to maintain a drift compensated mode selection result within a locking bandwidth of the PLL, and to minimize phase shifting from accumulating phase drift. The PLL detects a phase difference between the drift compensated mode selection result and a reference signal, for use in maintaining the PLL in a phase lock with the reference signal, in particular over wide operational temperature ranges.

Abstract: An optical performance monitor comprises a first stage configured to receive a multiplexed optical signal. The first stage is tunable over a period. The first stage periodically filters the multiplexed optical signal over an optical channel to produce a fine filtered optical signal. A second stage is coupled to the first stage and has a second-stage transfer function. The second stage receives the fine filtered optical signal and produces one or a plurality of interfered optical signal pairs. A third stage is coupled to the second stage and has a third-stage transfer function. The third stage receives the optical signal pairs and demultiplexes the optical signal pairs to produce a plurality of demultiplexed optical signals. The combination of the second-stage transfer function and the third-stage transfer function is flatter over the optical channel than the third-stage transfer function.

Abstract: An optical performance monitor comprises a first stage configured to receive a multiplexed optical signal. The first stage is tunable over a period. The first stage periodically filters the multiplexed optical signal over an optical channel to produce a fine filtered optical signal. A second stage is coupled to the first stage and has a second-stage transfer function. The second stage receives the fine filtered optical signal and produces one or a plurality of interfered optical signal pairs. A third stage is coupled to the second stage and has a third-stage transfer function. The third stage receives the optical signal pairs and demultiplexes the optical signal pairs to produce a plurality of demultiplexed optical signals. The combination of the second-stage transfer function and the third-stage transfer function is flatter over the optical channel than the third-stage transfer function.

Abstract: Digital serializer/deserializer circuitry includes a data path and a date eye monitoring path. The data path includes a first analog-to-digital converter (ADC) to sample incoming data at a first rate, first digital filter circuitry to filter output of the first ADC, and a data slicer coupled to output of the first digital filter circuitry to output data above a threshold. The monitoring path includes a second ADC to sample the incoming data at a second rate lower than the first rate and to take samples at varying points along the incoming data waveform, second digital filter circuitry to filter output of the second ADC, and another data slicer coupled to output of the second digital filter circuitry to output data above an adjustable threshold and to sweep through varying threshold values. Error rate circuitry compares outputs of the data slicers to determine a data eye error rate.

Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.