Patents by Inventor Mehmet Can Yildiz

Mehmet Can Yildiz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10460063
    Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10460064
    Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Wen-Hao Liu, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10460065
    Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li, Charles Jay Alpert
  • Patent number: 10460066
    Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Wen-Hao Liu, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10289795
    Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Charles Jay Alpert, Zhuo Li
  • Patent number: 10289792
    Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Wen-Hao Liu, Gracieli Posser, Mehmet Can Yildiz
  • Patent number: 10102328
    Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 16, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Zhuo Li, Charles Jay Alpert, Mehmet Can Yildiz
  • Patent number: 7073144
    Abstract: A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: July 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Gi-Joon Nam, Paul Gerard Villarrubia, Mehmet Can Yildiz