Patents by Inventor Mehmet Emin Aklik
Mehmet Emin Aklik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11340979Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.Type: GrantFiled: December 27, 2019Date of Patent: May 24, 2022Assignee: SEAGATE TECHNOLOGY LLCInventors: Mehmet Emin Aklik, Antoine Khoueir, Darshana H. Mehta, Nicholas Lien
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Patent number: 11175980Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory region, data loss and/or data recovery processes may be limited to improve drive performance and reliability.Type: GrantFiled: December 27, 2019Date of Patent: November 16, 2021Assignee: SEAGATE TECHNOLOGY LLCInventors: Mehmet Emin Aklik, Antoine Khoueir, Darshana H. Mehta, Nicholas Lien
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Patent number: 11086717Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.Type: GrantFiled: October 31, 2019Date of Patent: August 10, 2021Assignee: Seagate Technology LLCInventors: Mehmet Emin Aklik, Antoine Khoueir, Ara Patapoutian, Colin Hill, Kurt Walter Getreuer, Darshana H. Mehta
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Patent number: 11080129Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.Type: GrantFiled: December 27, 2019Date of Patent: August 3, 2021Assignee: SEAGATE TECHNOLOGY LLCInventors: Mehmet Emin Aklik, Antoine Khoueir, Darshana H. Mehta, Nicholas Lien
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Publication number: 20210200622Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Mehmet Emin AKLIK, Antoine KHOUEIR, Darshana H. MEHTA, Nicholas LIEN
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Publication number: 20210200623Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Mehmet Emin AKLIK, Antoine KHOUEIR, Darshana H. MEHTA, Nicholas LIEN
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Publication number: 20210200621Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Mehmet Emin AKLIK, Antoine KHOUEIR, Darshana H. MEHTA, Nicholas LIEN
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Publication number: 20210133025Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventors: Mehmet Emin Aklik, Antoine Khoueir, Ara Patapoutian, Colin Hill, Kurt Walter Getreuer, Darshana H. Mehta
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Patent number: 10901866Abstract: Systems and methods presented herein provide for failure detection and data recovery in a storage system. In one embodiment, a method operable in a storage system comprises locating failures in data blocks in storage area of a storage device, categorizing the failures into block groups, each block group comprising one or more data blocks having failures, and halting input/output (I/O) operations to data blocks in a first of the block groups due to the failures of the first block group. The method also includes detecting additional failures in one or more data blocks of other block groups remaining in the storage area, and determining when to fail the storage area of the storage device based on the detected failures.Type: GrantFiled: August 1, 2018Date of Patent: January 26, 2021Assignee: Seagate Technology, LLCInventors: Mehmet Emin Aklik, Ryan James Goss, Antoine Khoueir, Nicholas Odin Lien
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Publication number: 20190042379Abstract: Systems and methods presented herein provide for failure detection and data recovery in a storage system. In one embodiment, a method operable in a storage system comprises locating failures in data blocks in storage area of a storage device, categorizing the failures into block groups, each block group comprising one or more data blocks having failures, and halting input/output (I/O) operations to data blocks in a first of the block groups due to the failures of the first block group. The method also includes detecting additional failures in one or more data blocks of other block groups remaining in the storage area, and determining when to fail the storage area of the storage device based on the detected failures.Type: ApplicationFiled: August 1, 2018Publication date: February 7, 2019Inventors: Mehmet Emin Aklik, Ryan James Goss, Antoine Khoueir, Nicholas Odin Lien
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Patent number: 8324098Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.Type: GrantFiled: July 8, 2010Date of Patent: December 4, 2012Assignee: National Semiconductor CorporationInventors: Mehmet Emin Aklik, Thomas James Moutinho
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Publication number: 20120007245Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Inventors: Mehmet Emin Aklik, Thomas James Moutinho