Abstract: An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.

Abstract: A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

Abstract: A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

Abstract: We disclose a receiver circuit which may be used in mm-wave devices. The receiver circuit comprises a transimpedance amplifier comprising PMOS and NMOS transistors, wherein the back gate voltages provided to the transistors may be adjusted. By adjusting the back gate voltages during device operation, structural variations and temperature variations in the threshold voltages of the transistors may be minimized and the gain compression tolerance of the receiver circuit may be increased.

Abstract: A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.

Abstract: A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.

Abstract: A variable-gain RF amplifier arrangement whose input impedance is essentially independent of the selected gain is proposed, which has a large number of selectable elementary amplifiers, with an input signal being scaled and the input impedance being set to be the same by means of switchable current limiting elements upstream of the elementary amplifiers, which are associated with the elementary amplifiers. The circuit also has a low noise level, which is largely independent of the selected gain, and good linearity. A broadcast radio receiver as well as a receiver for receiving data signals using an amplifier according to the invention are also proposed.

Abstract: A variable-gain RF amplifier arrangement whose input impedance is essentially independent of the selected gain is proposed, which has a large number of selectable elementary amplifiers, with an input signal being scaled and the input impedance being set to be the same by means of switchable current limiting elements upstream of the elementary amplifiers, which are associated with the elementary amplifiers. The circuit also has a low noise level, which is largely independent of the selected gain, and good linearity. A broadcast radio receiver as well as a receiver for receiving data signals using an amplifier according to the invention are also proposed.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1.25-1.5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1,25-1,5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: The upconverter mixer circuit comprises a Gilbert cell with an LC-resonator tuned to the output frequency of the upconverter mixer circuit, and an output buffer. In a preferred embodiment the output buffer comprises a differential amplifier being emitter degenerated with inductances for a low-pass characteristic. The LC-resonator of the Gilbert cell as well as the inductances of the output amplifier are integrated in an integrated circuit together with the other parts of the upconverter mixer circuit and provide a first selection within the integrated circuit for the subsequent stages, for example an intermediate frequency filter of a double conversion TV tuner. When the upconverter mixer circuit is operated with a strong DC-current and hard switching, which is necessary for achieving low noise, strong high frequency parasitic currents are also generated.