Patents by Inventor Mehmet Mustafa

Mehmet Mustafa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8406365
    Abstract: A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 26, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Mehmet Mustafa Eker
  • Patent number: 8358159
    Abstract: Adaptive multi-band frequency calibration is provided for a phase-locked loop (PLL). A voltage controller oscillator (VCO) is initially selected nominally associated with first synthesized signal frequency, where the VCO is selected from a plurality of n VCOs, and each VCO is tunable across a band of synthesized signal frequencies. A lock detector compares a nominal first synthesized signal frequency to a reference signal frequency. In response to sensing a difference between the nominal first synthesizer and reference signal frequencies, an out-of-lock condition is asserted and a VCO is reselected from the plurality of n VCOs. A mid-point control voltage is supplied to a control voltage input of the reselected VCO. A difference is measured between a mid-point synthesized signal frequency and the reference signal frequency. If the difference is less than a first threshold, the reselected VCO is assigned to generate the first synthesized signal frequency.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 22, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Mehmet Mustafa Eker, Viet Do, Simon Pang
  • Patent number: 8121242
    Abstract: A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: February 21, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Mehmet Mustafa Eker, Simon Pang
  • Patent number: 8111785
    Abstract: A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: February 7, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Philip Michael Clovis, Michael Hellmer, Mehmet Mustafa Eker, Hongming An, Simon Pang
  • Patent number: 8094754
    Abstract: A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: January 10, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Mehmet Mustafa Eker, Simon Pang, Viet Linh Do, Hongming An, Philip Michael Clovis
  • Patent number: 8059778
    Abstract: A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer ?1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x?1).
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: November 15, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Mehmet Mustafa Eker, Simon Pang
  • Patent number: 7936853
    Abstract: A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: May 3, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventors: Simon Pang, Viet Linh Do, Mehmet Mustafa Eker
  • Patent number: 7720189
    Abstract: A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer?1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1 =Fref1/(x?1).
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: May 18, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Mehmet Mustafa Eker, Simon Pang
  • Publication number: 20100090734
    Abstract: A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage.
    Type: Application
    Filed: October 11, 2008
    Publication date: April 15, 2010
    Inventor: Mehmet Mustafa Eker
  • Patent number: 7692458
    Abstract: A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage.
    Type: Grant
    Filed: October 11, 2008
    Date of Patent: April 6, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Mehmet Mustafa Eker
  • Publication number: 20090147904
    Abstract: A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.
    Type: Application
    Filed: February 18, 2009
    Publication date: June 11, 2009
    Inventors: Viet Linh Do, Mehmet Mustafa Eker, Simon Pang
  • Publication number: 20090147901
    Abstract: A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.
    Type: Application
    Filed: February 18, 2009
    Publication date: June 11, 2009
    Inventors: Viet Linh Do, Philip Michael Clovis, Michael Hellmer, Mehmet Mustafa Eker, Hongming An, Simon Pang
  • Publication number: 20090122935
    Abstract: A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 14, 2009
    Inventors: Simon Pang, Viet Linh Do, Mehmet Mustafa Eker
  • Publication number: 20090092213
    Abstract: A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency.
    Type: Application
    Filed: December 3, 2008
    Publication date: April 9, 2009
    Inventors: Mehmet Mustafa Eker, Simon Pang, Viet Linh Do, Hongming An, Philip Michael Clovis
  • Publication number: 20080304610
    Abstract: A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.
    Type: Application
    Filed: August 20, 2008
    Publication date: December 11, 2008
    Inventors: Viet Linh Do, Mehmet Mustafa Eker
  • Publication number: 20080112525
    Abstract: A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer ?1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x?1).
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Inventors: Viet Linh Do, Mehmet Mustafa Eker, Simon Pang
  • Patent number: 7292667
    Abstract: A method for transmitting synchronization information with data, which data corresponds to a sequence of samples representative of a signal, includes detecting the occurrence of two consecutive equivalent samples and inserting a synchronization pattern for the second-occurring sample prior to transmission. At a receiving end, the incoming signal is monitored to detect the presence of the sync pattern and hold the value of the receiver output at the value of the immediately previous received sample. In this manner, the signal is reconstructed without degradation, and byte synchronization information is sent without any bandwidth loss.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: November 6, 2007
    Assignee: Verizon Laboratories Inc.
    Inventors: Walter Joseph Beriont, Mehmet Mustafa
  • Patent number: 7076056
    Abstract: Methods and apparatus for protecting quality of service during a process involving bridge tap in a communications system are described. Bridge tap may occur during system construction, central office re-concentration, replacement projects, upgrade projects, expansion projects, and installation of back-up cables, etc. Cables, with one end connected to a point in the system, and the other end left unterminated, result in bridge tap. In the bridge tap moderator of the present invention, a plurality of termination networks are attached to a modular connector such that a separate termination load is placed across each connector terminal pair for each corresponding wire pair of the cable. Communication lines can be easily attached to the moderator thereby easily, quickly, and efficiently eliminating bridge tap on a large number of wire pairs. The bridge tap modulator apparatus and method of use also minimize the amount of time bridge tap exists during cable and/or communication device installation.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: July 11, 2006
    Assignee: Verizon Laboratories Inc.
    Inventors: Michael F. Lane, Mehmet Mustafa
  • Patent number: 6876263
    Abstract: A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: April 5, 2005
    Assignee: Applied Micro Circuits Corporation
    Inventors: Wei Li, Thomas Clark Bryan, Harry Huy Dang, Mehmet Mustafa Eker
  • Patent number: 6566967
    Abstract: A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: May 20, 2003
    Assignee: Applied Micro Circuits Corporation
    Inventors: Sudhaker Reddy Anumula, Joseph J. Balardeta, Wei Fu, Paul Vanderbilt, Mehmet Mustafa Eker