Patents by Inventor Mehmet Onur Baykan

Mehmet Onur Baykan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456357
    Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 27, 2022
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Anupama Bowonder, William Hsu, Szuya S. Liao, Mehmet Onur Baykan, Tahir Ghani
  • Publication number: 20200006487
    Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Biswajeet Guha, Anupama Bowonder, William Hsu, Szuya S. Liao, Mehmet Onur Baykan, Tahir Ghani
  • Publication number: 20120199812
    Abstract: Silicon, silicon-germanium alloy, and germanium nanowire optoelectronic devices and methods for fabricating the same are provided. According to one embodiment, a P-I-N device is provided that includes a parallel array of intrinsic silicon, silicon-germanium or germanium nanowires located between a p+ contact and an n+ contact. In certain embodiments, the intrinsic silicon and germanium nanowires can be fabricated with diameters of less than 4.9 nm and 19 nm, respectively. In a further embodiment, vertically stacked silicon, silicon-germanium and germanium nanowires can be formed.
    Type: Application
    Filed: October 6, 2010
    Publication date: August 9, 2012
    Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Mehmet Onur Baykan, Toshikazu Nishida, Scott Emmet Thompson