Abstract: Various examples of thin film thermoelectric (TE) devices, their fabrication and applications are presented. In one example, a thin film TE device includes a first substrate including a void; a p-type TE element attached to the first substrate at a first end and extending over the void to a second end; an n-type TE element attached to the first substrate at a first end and extending over the void to a second end adjacent to the second end of the p-type TE element; and an interconnection coupling the second ends of the p-type TE element and the n-type TE element. In some examples, TE device layers can be vacuum sealed between a supporting substrate and a transparent substrate. A thermal spreader can include TE modules having a distribution of TE elements that operate in generating or cooling modes to cool IC or device hotspots using self-generated power.

Abstract: Various examples of thin film thermoelectric (TE) devices, their fabrication and applications are presented. In one example, a thin film TE device includes a first substrate including a void; a p-type TE element attached to the first substrate at a first end and extending over the void to a second end; an n-type TE element attached to the first substrate at a first end and extending over the void to a second end adjacent to the second end of the p-type TE element; and an interconnection coupling the second ends of the p-type TE element and the n-type TE element. In some examples, TE device layers can be vacuum sealed between a supporting substrate and a transparent substrate. A thermal spreader can include TE modules having a distribution of TE elements that operate in generating or cooling modes to cool IC or device hotspots using self-generated power.

Abstract: The present invention relates to a system for enabling persons who are or are not subscribers of institutions making financial transaction to realize person authentication by means of fingerprint and/or retina information and/or face detection in order to carry out transaction over financial institution. The inventive system consists of mobile device, financial institution unit, identity authentication unit and authentication server.

Abstract: Flexible thermoelectric generators and methods of manufacturing are disclosed. In one embodiment, a flexible thermoelectric generator includes a plurality of pillars, a first and a second plurality of flexible interconnects, and a flexible material. The plurality of pillars having a first side and a second side. The first plurality of flexible interconnects electrically connecting pairs of the plurality of pillars on the first side. The second plurality of flexible interconnects electrically connecting the pairs of plurality of pillars on the second side. The first and the second plurality of flexible interconnects alternate among the pairs of plurality of pillars to form an electrical circuit having a first end and a second end. The flexible material covering the first and second plurality of flexible interconnects and having an external surface. The flexible material is configured to conduct thermal energy from the external surface to the plurality of pillars.

Abstract: Flexible thermoelectric generators and methods of manufacturing are disclosed. In one embodiment, a flexible thermoelectric generator includes a plurality of pillars, a first and a second plurality of flexible interconnects, and a flexible material. The plurality of pillars having a first side and a second side. The first plurality of flexible interconnects electrically connecting pairs of the plurality of pillars on the first side. The second plurality of flexible interconnects electrically connecting the pairs of plurality of pillars on the second side. The first and the second plurality of flexible interconnects alternate among the pairs of plurality of pillars to form an electrical circuit having a first end and a second end. The flexible material covering the first and second plurality of flexible interconnects and having an external surface. The flexible material is configured to conduct thermal energy from the external surface to the plurality of pillars.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.

Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: This invention relates to a method of detecting and diagnosing neurological disease or dysfunction using antibodies against a neurological form of Pancreatic Thread Protein (nPTP). Specifically, this invention is directed to a method of diagnosing Alzheimer's Disease, Down's Syndrome, and other neurological diseases or dysfunctions by using monoclonal antibodies, combination of those monoclonal antibodies or nucleic acid probes, to detect nPTP. The invention also relates to a recombinant DNA molecule encoding PTP and to the substantially pure form of nPTP. The invention additionally relates to a method of diagnosing pancreatic disease using antibodies against Pancreatic Thread Protein.

Abstract: The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

Abstract: The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure.

Abstract: The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

Abstract: The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure.

Abstract: A method for the determination of a free protein subunit of a quaternary protein in a sample, which comprises:(a) contacting a sample with a first immunological binding partner which is or will be bound to a carrier, wherein the first immunological binding partner binds epitopic determinants bindable only on the free protein subunit;(b) incubating the components of step (a) for a period of time and under conditions sufficient to form an immune complex between the free protein subunit, the first immunological binding partner, and the carrier;(c) separating the carrier of step (b) from the sample;(d) adding to the carrier of step (c), a detectably-labeled second immunological binding partner, wherein the second immunological binding partner binds epitopic determinants bindable on both the free protein subunit and the quaternary protein; and(e) determining the detectably-labeled second immunological binding partner in the carrier or in liquid phase.

Abstract: A highly sensitive and specific monoclonal-immuno-radiometric assay (M-IRMA) for hCG, using monoclonal antibodies (Mabs) directed against a 37-amino acid synthetic polypeptide analogous to the carboxyl terminus (CTP) of beta-hCG. Accordingly, in one embodiment, a method is described for the determination of human chorionic gonadotrThe present invention was made utilizing funds of the United States Government. The U.S. government is therefore granted a royalty-free, non-exclusive, world wide, paid-up license in this invention.